AD7707 datasheet(20/40 Pages) AD

20 / 40 page

REV. A

AD7707

–20–

ANALOG INPUT

Analog Input Ranges

The AD7707 contains two low level pseudo-differential analog

input channels AIN1 and AIN2. These input pairs provide

programmable-gain, differential input channels that can handle

either unipolar or pseudo bipolar input signals. It should be

noted that the bipolar input signals are referenced to the

LOCOM input. The AD7707 also has a high level analog input

channel AIN 3 which is referenced to HICOM. Figure 11

shows the input structure on the high level input channel.

In normal 5 V operation VBIAS is normally connected to 2.5 V

and HICOM is connected to AGND. This arrangement ensures

that the voltages seen internally are within the common-mode

range of the buffer in buffered mode and within the supply

range in unbuffered mode. This device can be programmed to

operate in either buffered or unbuffered mode via the BUF bit

in the setup register. Note that the signals on AIN3 are with

respect to the HICOM input and not with respect to AGND or

DGND.

The differential voltage seen by the AD7707 when using the

high level input channel is the difference between AIN3(+) and

AIN3(–) on the mux as shown in Figure 11.

AIN3(+) = (AIN3 + 6

× VBIAS+ V (HICOM))/8

AIN3

MUX

VBIAS

1R = 5k

HICOM

AIN3(–)

AIN3(+)

Figure 11. AIN3 Input Structure

AIN3(–) = V (HICOM) + 0.75

× (VBIAS – V (HICOM))

In unbuffered mode, the common-mode range of the low level

input channels is from AGND – 100 mV to AVDD + 30 mV.

This means that in unbuffered mode the part can handle both

unipolar and bipolar input ranges for all gains. Absolute volt-

ages of AGND – 100 mV can be accommodated on the analog

inputs without degradation in performance, but leakage current

increases appreciably with increasing temperature. In buffered

mode, the analog inputs can handle much larger source imped-

ances, but the absolute input voltage range is restricted to be-

tween AGND + 50 mV to AVDD – 1.5 V which also places

restrictions on the common-mode range. This means that in

buffered mode there are some restrictions on the allowable

gains for bipolar input ranges. Care must be taken in setting up

the common-mode voltage and input voltage range so that the

above limits are not exceeded, otherwise there will be a degra-

dation in linearity performance.

In unbuffered mode, the analog inputs look directly into the

7 pF input sampling capacitor, CSAMP. The dc input leakage

current in this unbuffered mode is 1 nA maximum. As a result,

the analog inputs see a dynamic load that is switched at the

input sample rate (see Figure 12). This sample rate depends on

master clock frequency and selected gain. CSAMP is charged to

AIN(+) and discharged to AIN(–) every input sample cycle.

The effective on-resistance of the switch, RSW, is typically 7 kΩ.

CSAMP must be charged through RSW and any additional source

impedances every input sample cycle. Therefore, in unbuffered

mode, source impedances mean a longer charge time for CSAMP

and this may result in gain errors on the part. Table XVI shows

the allowable external resistance/capacitance values, for unbuffered

mode, such that no gain error to the 16-bit level is introduced

on the part. Note that these capacitances are total capacitances

on the analog input. This external capacitance includes 10 pF

from pins and lead frame of the device.

AIN(+)

AIN(–)

SWITCHING FREQUENCY DEPENDS ON

fCLKIN AND SELECTED GAIN

RSW (7k

TYP)

CSAMP

(7pF)

FIRST

INTEGRATOR

HIGH INPUT

IMPEDANCE

VDD/2

Figure 12. Unbuffered Analog Input Structure

Table XVI. External R, C Combination for No 16-Bit Gain

Error on Low Level Input Channels (Unbuffered Mode Only)

External Capacitance (pF)

Gain

100

500

1000

5000

368 k

Ω

90.6 k

Ω 54.2 kΩ 14.6 kΩ 8.2 kΩ 2.2 kΩ

177.2 k

Ω 44.2 kΩ 26.4 kΩ 7.2 kΩ 4 kΩ

1.12 k

Ω

82.8 k

Ω

21.2 k

Ω 12.6 kΩ 3.4 kΩ 1.94 kΩ 540 Ω

8–128

35.2 k

Ω

9.6 k

Ω

5.8 k

Ω 1.58 Ω 880 Ω

240

Ω

EXTERNAL CAPACITANCE – pF

10000

100

1000

100

150

200

250

300

350

400

GAIN = 1

GAIN = 4

GAIN = 8-128

GAIN = 2

Figure 13. External R, C Combination for No 16-Bit Gain

Error on Low Level Input Channels (Unbuffered Mode Only)

In buffered mode, the analog inputs look into the high imped-

ance inputs stage of the on-chip buffer amplifier. CSAMP is

charged via this buffer amplifier such that source impedances do

not affect the charging of CSAMP. This buffer amplifier has an

offset leakage current of 1 nA. In buffered mode, large source

impedances result in a small dc offset voltage developed across

the source impedance, but not in a gain error.

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