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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PCAL9539APW датащи(PDF) 13 Page - NXP Semiconductors |
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PCAL9539APW датащи(HTML) 13 Page - NXP Semiconductors |
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13 / 48 page  PCAL9539A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 3 October 2012 13 of 48 NXP Semiconductors PCAL9539A 16-bit I2C-bus and SMBus low power I/O port with interrupt and reset 6.3 I/O port When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output port register. In this case, there are low-impedance paths between the I/O pin and either VDD or VSS. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation. At power-on reset, all registers return to default values. Fig 6. Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7) INTERRUPT MASK VDD P0_0 to P0_7 P1_0 to P1_7 output port register data configuration register DQ CK Q data from shift register write configuration pulse output port register DQ CK write pulse polarity inversion register DQ CK data from shift register write polarity pulse input port register DQ CK read pulse input port register data 002aah428 FF data from shift register FF FF FF Q1 Q2 VSS to INT PULL-UP/PULL-DOWN CONTROL ESD protection diode 100 kΩ VDD ESD protection diode input port latch DQ EN LATCH read pulse input latch register DQ CK FF data from shift register write input latch pulse |
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