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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD73322LAST датащи(PDF) 2 Page - Analog Devices |
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AD73322LAST датащи(HTML) 2 Page - Analog Devices |
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2 / 40 page  REV. 0 –2– AD73322L–SPECIFICATIONS1 (AVDD = 3 V 10%; DVDD = 3 V 10%; DGND = AGND = 0 V, fDMCLK = 16.384 MHz, fSAMP = 8 kHz; TA = TMIN to TMAX, unless otherwise noted.) A, Y Versions Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE REFCAP Absolute Voltage, VREFCAP 1.08 1.2 1.32 V REFCAP TC 50 ppm/ °C 0.1 µF Capacitor Required from REFOUT REFCAP to AGND2 Typical Output Impedance 130 Ω Absolute Voltage, VREFOUT 1.08 1.2 1.32 V Unloaded Minimum Load Resistance 1 k Ω Maximum Load Capacitance 100 pF INPUT AMPLIFIER Offset ±1.0 mV Maximum Output Swing 1.578 V Max Output Swing = (1.578/1.2) × VREFCAP Feedback Resistance 50 k Ω fC = 32 kHz Feedback Capacitance 100 pF ANALOG GAIN TAP Gain at Maximum Setting +1 Gain at Minimum Setting –1 Gain Resolution 5 Bits Gain Step Size = 0.0625 Gain Accuracy ±1.0 % Output Unloaded Settling Time 1.0 µs Tap Gain Change of –FS to +FS Delay 0.5 µs ADC SPECIFICATIONS DAC Unloaded Maximum Input Range at VIN 2, 3 1.578 V p-p Measured Differentially –2.85 dBm Max Input = (1.578/1.2) × VREFCAP Nominal Reference Level at VIN 1.0954 V p-p Measured Differentially (0 dBm0) –6.02 dBm Absolute Gain PGA = 0 dB –2.0 –0.7 +0.5 dB 1.0 kHz, 0 dBm0 Gain Tracking Error ±0.1 dB 1.0 kHz, +3 dBm0 to –50 dBm0 Signal to (Noise + Distortion) Refer to TPC 1. PGA = 0 dB 70 78 dB 300 Hz to 3400 Hz; fSAMP = 8 kHz, PUIA = 0 79 dB 300 Hz to 3400 Hz; fSAMP = 8 kHz, PUIA = 1 77.5 dB 0 Hz to fSAMP/2; fSAMP = 8 kHz Total Harmonic Distortion PGA = 0 dB –86 –75 dB 300 Hz to 3400 Hz; fSAMP = 8 kHz Intermodulation Distortion –61 dB PGA = 0 dB Idle Channel Noise Crosstalk –72 dBm0 PGA = 0 dB ADC-to-DAC –107 dB ADC Input Signal Level: 1.0 kHz, 0 dBm0 DAC Input at Idle ADC-to-ADC –92 dB ADC1 Input Signal Level: 1.0 kHz, 0 dBm0 ADC2 Input at Idle. Input Amplifiers Bypassed –93 dB Input Amplifiers Included in Input Channel DC Offset –20 0 +20 mV PGA = 0 dB Power Supply Rejection –65 dB Input Signal Level at AVDD and DVDD Pins: 1.0 kHz, 100 mV p-p Sine Wave Group Delay 4, 5 25 µs Input Resistance at PGA 2, 4, 6 20 k Ω Input Amplifiers Bypassed DIGITAL GAIN TAP Gain at Maximum Setting +1 Gain at Minimum Setting –1 Gain Resolution 16 Bits Tested to 5 MSBs of Settings Delay 25 µs Includes DAC Delay Settling Time 100 µs Tap Gain Change from –FS to +FS; Includes DAC Settling Time |
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