AD73322LAST datasheet(13/40 Pages) AD

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AD73322L

–13–

Interpolation Filter

The anti-imaging interpolation filter is a sinc-cubed digital filter

that up-samples the 16-bit input words from the input sample

rate to a rate of DMCLK/8, while filtering to attenuate images

produced by the interpolation process. Its Z transform is given as:

[(1 – Z

–N)/(1 – Z –1)]3

where N is determined by the sampling rate (N = 32 @ 64 kHz .

. . N = 256 @ 8 kHz). The DAC receives 16-bit samples from

the host DSP processor at the programmed sample rate of

DMCLK/N. If the host processor fails to write a new value to

the serial port, the existing (previous) data is read again. The

data stream is filtered by the anti-imaging interpolation filter,

but there is an option to bypass the interpolator for the mini-

mum group delay configuration by setting the IBYP bit (CRE:5)

of Control register E. The interpolation filter has the same char-

acteristics as the ADC’s antialiasing decimation filter.

The output of the interpolation filter is fed to the DAC’s digital

sigma-delta modulator, which converts the 16-bit data to 1-bit

samples at a rate of DMCLK/8. The modulator noise-shapes

the signal so that errors inherent to the process are minimized in

the passband of the converter. The bit-stream output of the

sigma-delta modulator is fed to the single-bit DAC where it is

converted to an analog voltage.

Analog Smoothing Filter and PGA

The output of the single-bit DAC is sampled at DMCLK/8,

therefore it is necessary to filter the output to reconstruct the

low frequency signal. The decoder’s analog smoothing filter

consists of a continuous-time filter preceded by a third-order

switched-capacitor filter. The continuous-time filter forms part

of the output programmable gain amplifier (PGA). The PGA

can be used to adjust the output signal level from –15 dB to

+6 dB in 3 dB steps, as shown in Table IV. The PGA gain is

set by bits OGS0, OGS1 and OGS2 (CRD:4-6) in Control

Table IV. PGA Settings for the Decoder Channel

OGS2

OGS1

OGS0

Gain (dB)

–3

–6

–9

–12

–15

Differential Output Amplifiers

The decoder has a differential analog output pair (VOUTP and

VOUTN). The output channel can be muted by setting the

MUTE bit (CRD:7) in Control Register D. The output signal is

dc-biased to the codec’s on-chip voltage reference.

Voltage Reference

The AD73322L reference, REFCAP, is a bandgap reference

that provides a low noise, temperature-compensated reference

to the DAC and ADC. A buffered version of the reference is

also made available on the REFOUT pin and can be used to

bias other external analog circuitry. The reference has a default

nominal value of 1.2 V.

The reference output (REFOUT) can be enabled for biasing

external circuitry by setting the RU bit (CRC:6) of CRC.

INVERTING

OP AMPS

ANALOG

LOOP-BACK

SELECT

INVERT

SINGLE-

ENDED

ENABLE

GAIN

+6/–15dB

PGA

CONTINUOUS

TIME

LOW-PASS

FILTER

VREF

VINN1

VINP1

VFBP1

VOUTP1

VOUTN1

REFCAP

REFOUT

REFERENCE

AD73322L

VREF

VFBN1

ANALOG GAIN

TAP

0/38dB

PGA

Figure 9. Analog Input/Output Section

Analog and Digital Gain Taps

The AD73322L features analog and digital feedback paths

between input and output. The amount of feedback is deter-

mined by the gain setting which is programmed in the control

registers. This feature can typically be used for balancing the

effective impedance between input and output when used in

Subscriber Line Interface Circuit (SLIC) interfacing.

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