ACT8934A datasheet(27/45 Pages) ACTIVE-SEMI

27 / 45 page

ACT8934A

Rev 1, 22-Oct-12

Innovative Power

ActivePMU

TM and ActivePathTM are trademarks of Active-Semi.

2CTM is a trademark of NXP.

- 27 -

www.active-semi.com

The ACT8934A is optimized for use in applications

using the S3C2416/S3C2450 processor, supporting

both the power domains as well as the signal

interface for these processors.

While the ACT8934A supports many possible

configurations for powering these processors, one

of the most common configurations is detailed in

this datasheet. In general, this document refers to

the ACT8934A pin names and functions. However,

in cases where the description of interconnections

between these devices benefits by doing so, both

the ACT8934A pin names and the Samsung

processor pin names are provided. When this is

done, the S3C2416/S3C2450 pin names are

located after the ACT8934A pin names, and are

italicized and located inside parentheses. For

example, PWREN (PWR_EN) refers to the logic

signal applied to the ACT8934A's PWREN input,

identifying

that

driven

from

the

S3C2416/S3C2450's PWR_EN output. Likewise,

OUT1 (VDD_IO) refers to ACT8934A's OUT1 pin,

identifying

that

connected

the

S3C2416/S3C2450's VDD_IO power domain.

SYSTEM CONTROL INFORMATION

Interfacing with the Samsung S3C2416/S3C2450

Table 3:

ACT8934A and Samsung S3C2416/S3C2450 Power Modes

Table 2:

ACT8934A and Samsung S3C2416/S3C2450 Power Domains

POWER DOMAIN

ACT8934A CHANNEL

TYPE

DEFAULT VOLTAGE

CURRENT CAPABILITY

VDD_IO

REG1

DC/DC

3.3V/3.3V

900mA

VDD_MEM

REG2

DC/DC

1.8V/1.8V

700mA

VDD_SRAM

VDDiarm

REG3

DC/DC

1.3V/1.3V

VDDi

VDDA_xPLL

REG4

LDO

1.2V

150mA

VDD_Alive

REG5

LDO

1.2V

150mA

VDDI_UDEV

REG6

LDO

1.2V

250mA

VDDA33x

REG7

LDO

3.3V

250mA

900mA

POWER

MODE

CONTROL STATE

POWER DOMAIN STATE

QUIESCENT

CURRENT

ALL ON

PWRHLD is asserted, PWREN is asserted,

REG6 and REG7 are enabled by I2C

REG1, REG2, REG3, REG4, REG5,

REG6 and REG7 are all on

420µA

NORMAL

PWRHLD is asserted, PWREN is asserted,

REG6 and REG7 are disabled by I2C

REG1, REG2, REG3, REG4 and

REG5 are on. REG6 and REG7 are off

350µA

SLEEP

PWRHLD is asserted, PWREN is de-asserted,

REG6 and REG7 are disabled by I2C

REG1, REG2 and REG5 are on. REG3,

REG4, REG6 and REG7 are off

250µA

ALL OFF

PWRHLD is de-asserted, PWREN is de-

asserted, REG6 and REG7 are disabled by I2C

REG1, REG2, REG3, REG4, REG5,

REG6 and REG7 are all off

<18µA

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