AD1380

–5–

REV. B

SAR parallel bits, STATUS flip-flops and the gated clock in-

hibit signal are initialized on the trailing edge of the CONVERT

reset unconditionally. This sequence continues until the Bit 16

indicating that the conversion is complete and the parallel

output data is valid. Resetting the STATUS flag restores the

gated clock inhibit signal, forcing the clock output to the low

Logic “0” state. Note that the clock remains low until the next

conversion.

Corresponding parallel data bits become valid on the same

positive-going clock edge.

DIGITAL OUTPUT DATA

Both parallel and serial data from TTL storage registers is in

negative true form (Logic “1” = 0 V and Logic “0” = 2.4 V).

Parallel data output coding is complementary binary for unipolar

ranges and complementary offset binary for bipolar ranges.

Parallel data becomes valid at least 20 ns before the STATUS

flag returns to Logic “0,” permitting parallel data transfer to be

clocked on the “1” to “0” transition of the STATUS flag (see

Figure 6).

Figure 6. LSB Valid to Status Low

Serial data coding is complementary binary for unipolar input

ranges and complementary offset binary for bipolar input

ranges. Serial output is by bit (MSB first, LSB last) in NRZ

(non-return-to-zero) format. Serial and parallel data outputs

change state on positive-going clock edges. Serial data is guaran-

teed valid 120 ns after the rising clock edges, permitting serial

data to be clocked directly into a receiving register on the

negative-going clock edges as shown in Figure 7. There are 17

negative-going clock edges in the complete 16-bit conversion

cycle. The first negative edge shifts an invalid bit into the regis-

ter, which is shifted out on the last negative-going clock edge.

All serial data bits will have been correctly transferred and be in

the receiving shift register locations shown at the completion of

the conversion period.

Figure 7. Clock High to Serial Out Valid

INPUT SCALING

The AD1380 inputs should be scaled as close to the maximum

input signal range as possible in order to utilize the maximum

signal resolution of the A/D converter. Connect the input signal

as shown in Table I. See Figure 8 for circuit details.

Figure 8. AD1380 Input Scaling Circuit

Table I. AD1380 Input Scaling Connections

Input

Connect

Connect

Connect

Signal

Output

Pin 4

Pin 7

Input

Line

Code

to Pin

to

Signal to

±10 V

COB

5

Input Signal

7

±5 V

COB

5

Open

6

±2.5 V

COB

5

Pin 5

6

0 V to +5 V

CSB

NC

Pin 5

6

0 V to +10 V

CSB

NC

Open

6

NOTE

Pin 5 is extremely sensitive to noise and should be guarded by analog common.