AD1380

–4–

REV. B

GAIN ADJUSTMENT

The gain adjust circuit consists of a 100 ppm/

°C potentiometer

connected across

±V

300 k

Ω resistor to the gain adjust Pin 3 as shown in Figure 2.

If no external trim adjustment is desired, Pin 5 (OFFSET ADJ)

and Pin 3 (GAIN ADJ) may be left open.

Figure 2. Gain Adjustment Circuit (

±0.2% FSR)

OFFSET ADJUSTMENT

The zero adjust circuit consists of a 100 ppm/

°C potentiometer

connected across

±V

1.8 M

Ω resistor to Comparator Input Pin 5 for all ranges. As

shown in Figure 3, the tolerance of this fixed resistor is not

critical, and a carbon composition type is generally adequate.

Using a carbon composition resistor having a –1200 ppm/

°C

×

× 1200 ppm/°C = 2.3 ppm/°C of FSR, if the

OFFSET ADJ potentiometer is set at either end of its adjust-

ment range. Since the maximum offset adjustment required is

typically no more than

±16 LSB

offset summing resistor typically contributes no more than

1 ppm/

°C of FSR offset tempco.

Figure 5. Timing Diagram (Binary Code 0110011101 111010)

Figure 3. Offset Adjustment Circuit (

±0.3% FSR)

An alternate offset adjust circuit, which contributes negligible

offset tempco if metal film resistors (tempco <100 ppm/

°C) are

used, is shown in Figure 4.

Figure 4. Low Tempco Zero Adjustment Circuit

In either adjust circuit, the fixed resistor connected to Pin 5

should be located close to this pin to keep the pin connection

runs short. Comparator Input Pin 5 is quite sensitive to external

noise pickup and should be guarded by analog common.

TIMING

The timing diagram is shown in Figure 5. Receipt of a CON-

VERT START signal sets the STATUS flag, indicating conver-

sion in progress. This, in turn, removes the inhibit applied to

the gated clock permitting it to run through 17 cycles. All the