41594B datasheet(151/372 Pages) MICROCHIP

151 / 372 page

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Preliminary

DS41594B-page 151

PIC12LF1840T48A

19.2

Comparator Control

The comparator has two control registers: CM1CON0

and CM1CON1.

The CM1CON0 register (see Register 19-1) contains

Control and Status bits for the following:

• Enable

•Output selection

• Output polarity

• Speed/Power selection

• Hysteresis enable

• Output synchronization

The CM1CON1 register (see Register 19-2) contains

Control bits for the following:

• Interrupt enable

• Interrupt edge polarity

• Positive input channel selection

• Negative input channel selection

19.2.1

COMPARATOR ENABLE

Setting the C1ON bit of the CM1CON0 register enables

the comparator for operation. Clearing the C1ON bit

disables the comparator resulting in minimum current

consumption.

19.2.2

COMPARATOR OUTPUT

SELECTION

The output of the comparator can be monitored by

reading either the C1OUT bit of the CM1CON0 register

or the MC1OUT bit of the CMOUT register. In order to

make the output available for an external connection,

the following conditions must be true:

• C1OE bit of the CM1CON0 register must be set

• Corresponding TRIS bit must be cleared

• C1ON bit of the CM1CON0 register must be set

19.2.3

COMPARATOR OUTPUT POLARITY

Inverting the output of the comparator is functionally

equivalent to swapping the comparator inputs. The

polarity of the comparator output can be inverted by

setting the C1POL bit of the CM1CON0 register.

Clearing the C1POL bit results in a non-inverted output.

Table 19-1 shows the output state versus input

conditions, including polarity control.

19.2.4

COMPARATOR SPEED/POWER

SELECTION

The trade-off between speed or power can be opti-

mized during program execution with the C1SP control

bit. The default state for this bit is ‘1’ which selects the

normal speed mode. Device power consumption can

be optimized at the cost of slower comparator propaga-

tion delay by clearing the C1SP bit to ‘0’.

Note 1: The C1OE bit of the CM1CON0 register

overrides the PORT data latch. Setting

the C1ON bit of the CM1CON0 register

has no impact on the port override.

2: The internal output of the comparator is

latched with each instruction cycle.

Unless otherwise specified, external

outputs are not latched.

TABLE 19-1:

COMPARATOR OUTPUT

STATE VS. INPUT

CONDITIONS

Input Condition

C1POL

C1OUT

C1VN > C1VP

C1VN < C1VP

C1VN > C1VP

C1VN < C1VP

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