41594B datasheet(146/372 Pages) MICROCHIP

146 / 372 page

PIC12LF1840T48A

DS41594B-page 146

Preliminary

 2011-2012 Microchip Technology Inc.

SRCON1: SR LATCH CONTROL 1 REGISTER

R/W-0/0

SRSPE

SRSCKE

Reserved

SRSC1E

SRRPE

SRRCKE

Reserved

SRRC1E

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

SRSPE: SR Latch Peripheral Set Enable bit

1 = SR Latch is set when the SRI pin is high

0 = SRI pin has no effect on the set input of the SR Latch

bit 6

SRSCKE: SR Latch Set Clock Enable bit

1 = Set input of SR Latch is pulsed with SRCLK

0 = SRCLK has no effect on the set input of the SR Latch

bit 5

Reserved: Read as ‘0’. Maintain this bit clear.

bit 4

SRSC1E: SR Latch C1 Set Enable bit

1 = SR Latch is set when the C1 Comparator output is high

0 = C1 Comparator output has no effect on the set input of the SR Latch

bit 3

SRRPE: SR Latch Peripheral Reset Enable bit

1 = SR Latch is reset when the SRI pin is high

0 = SRI pin has no effect on the Reset input of the SR Latch

bit 2

SRRCKE: SR Latch Reset Clock Enable bit

1 = Reset input of SR Latch is pulsed with SRCLK

0 = SRCLK has no effect on the Reset input of the SR Latch

bit 1

Reserved: Read as ‘0’. Maintain this bit clear.

bit 0

SRRC1E: SR Latch C1 Reset Enable bit

1 = SR Latch is reset when the C1 Comparator output is high

0 = C1 Comparator output has no effect on the Reset input of the SR Latch

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