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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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41594B датащи(PDF) 220 Page - Microchip Technology |
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41594B датащи(HTML) 220 Page - Microchip Technology |
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220 / 372 page  PIC12LF1840T48A DS41594B-page 220 Preliminary 2011-2012 Microchip Technology Inc. 25.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in full power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP1 clock is much faster than the system clock. In Slave mode, when MSSP1 interrupts are enabled, after the master completes sending data, an MSSP1 interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSP1 interrupts should be disabled. In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmis- sion/reception will remain in that state until the device wakes. After the device returns to Run mode, the mod- ule will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSP1 interrupt flag bit will be set and if enabled, will wake the device. TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — —ANSA4 — ANSA2 ANSA1 ANSA0 114 APFCON RXDTSEL SDOSEL SSSEL — T1GSEL TXCKSEL P1BSEL CCP1SEL 110 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 83 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 84 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 86 SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 213* SSP1CON1 WCOL SSP1OV SSP1EN CKP SSP1M<3:0> 259 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 261 SSP1STAT SMP CKE D/A P S R/W UA BF 258 TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 113 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP1 in SPI mode. * Page provides register information. |
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