41594B datasheet(213/372 Pages) MICROCHIP

213 / 372 page

 2011-2012 Microchip Technology Inc.

Preliminary

DS41594B-page 213

PIC12LF1840T48A

FIGURE 25-4:

SPI MASTER AND MULTIPLE SLAVE CONNECTION

25.2.1 SPI MODE REGISTERS

The MSSP1 module has five registers for SPI mode

operation. These are:

• MSSP1 STATUS register (SSP1STAT)

• MSSP1 Control Register 1 (SSP1CON1)

• MSSP1 Control Register 3 (SSP1CON3)

• MSSP1 Data Buffer register (SSP1BUF)

• MSSP1 Address register (SSP1ADD)

• MSSP1 Shift register (SSP1SR)

(Not directly accessible)

SSP1CON1 and SSP1STAT are the control and

STATUS registers in SPI mode operation. The

SSP1CON1 register is readable and writable. The

lower 6 bits of the SSP1STAT are read-only. The upper

two bits of the SSP1STAT are read/write.

In one SPI master mode, SSP1ADD can be loaded

with a value used in the Baud Rate Generator. More

information on the Baud Rate Generator is available in

Section 25.7 “Baud Rate Generator”.

SSP1SR is the shift register used for shifting data in

and out. SSP1BUF provides indirect access to the

SSP1SR register. SSP1BUF is the buffer register to

which data bytes are written, and from which data

bytes are read.

In receive operations, SSP1SR and SSP1BUF

together create a buffered receiver. When SSP1SR

receives a complete byte, it is transferred to SSP1BUF

and the SSP1IF interrupt is set.

During transmission, the SSP1BUF is not buffered. A

write to SSP1BUF will write to both SSP1BUF and

SSP1SR.

SPI Master

SCK

SDO

SDI

General I/O

SCK

SDI

SDO

SPI Slave

SCK

SDI

SDO

SPI Slave

SCK

SDI

SDO

SPI Slave

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