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CY8C56LP датащи(PDF) 8 Page - Cypress Semiconductor

номер детали CY8C56LP
подробное описание детали  Programmable System-on-Chip (PSoC짰)
PDF  120 Pages
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производитель  CYPRESS [Cypress Semiconductor]
домашняя страница  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C56LP датащи(HTML) 8 Page - Cypress Semiconductor

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PRELIMINARY
PSoC® 5LP: CY8C56LP Family
Datasheet
Document Number: 001-84935 Rev. **
Page 8 of 120
Figure 2-5. Example Schematic for 100-pin TQFP Part with Power Connections
Note
The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended,
as shown in Figure 2-6.
Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
VSSB
10
IND
11
VBOOST
12
VBAT
13
VSSD
14
XRES
15
VCCA
63
VSSA
64
VDDA
65
VSSD
66
SIO, P12[2]
67
SIO, P12[3]
68
P4[0]
69
P4[1]
70
OA2OUT, P0[0]
71
OA0OUT, P0[1]
72
OA0+, SAR1REF, P0[2]
73
OA0-, REF0, P0[3]
74
VDDIO0
75
P5[0]
16
P5[1]
17
P5[2]
18
P5[3]
19
P1[0], SWDIO, TMS
20
P1[1], SWDCK, TCK
21
P1[2]
22
P1[3], SWV, TDO
23
P1[4], TDI
24
P1[5], NTRST
25
P6[7]
9
P2[5]
1
P2[6]
2
P2[7]
3
P12[4], SIO
4
P12[5], SIO
5
P6[4]
6
P6[5]
7
P6[6]
8
OA1OUT, P3[6]
51
OA3OUT, P3[7]
52
SIO, P12[0]
53
SIO, P12[1]
54
KHZXOUT, P15[2]
55
KHZXIN, P15[3]
56
NC
57
NC
58
NC
59
NC
60
NC
61
NC
62
VSSD
VDDA
VCCA
VSSD
VSSA
VSSA
VSSD
VSSD
VSSD
VSSD
0.1 UF
C8
VSSD
VDDD
VDDD
VDDD
VDDD
VDDD
VSSD
1 UF
C9
0.1 UF
C10
0.1 UF
C11
0.1 UF
C16
0.1 UF
C12
0.1 UF
C6
0.1 UF
C2
1 UF
C15
1 UF
C1
VSSD
VDDD
VSSD
VDDA
VSSD
VCCD
1 UF
C17
VSSA
VDDA
VD D D
VS SD
VD D A
VS SA
VS SD
Plan e
VS SA
Plan e



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