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CY8C56LP датащи(PDF) 7 Page - Cypress Semiconductor

номер детали CY8C56LP
подробное описание детали  Programmable System-on-Chip (PSoC짰)
PDF  120 Pages
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производитель  CYPRESS [Cypress Semiconductor]
домашняя страница  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C56LP датащи(HTML) 7 Page - Cypress Semiconductor

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PRELIMINARY
PSoC® 5LP: CY8C56LP Family
Datasheet
Document Number: 001-84935 Rev. **
Page 7 of 120
Figure 2-4. 100-pin TQFP Part Pinout
Figure 2-5 and Figure 2-6 on page 8 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal
analog performance on a 2-layer board.
The two pins labeled VDDD must be connected together.
The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-5 on page 8 and Power
System on page 24. The trace between the two VCCD pins should be as short as possible.
The two pins labeled VSSD must be connected together.
For information on circuit board layout issues for mixed signals, refer to the application note AN57821 - Mixed Signal Circuit Board
Layout Considerations for PSoC® 3 and PSoC 5.
TQFP
(TRACEDATA[1] , GPIO)P2[5]
(TRACEDATA[2] , GPIO)P2[6]
(TRACEDATA[3] , GPIO)P2[7]
(I2C0 : SCL, SIO )P12[4]
(I2C0 : SDA, SIO )P12[5]
(GPIO)P6[4]
(GPIO)P6[5]
(GPIO)P6[6]
(GPIO)P6[7]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
(GPIO)P5[0]
(GPIO)P5[1]
(GPIO)P5[2]
(GPIO)P5[3]
( TMS, SWDIO, GPIO)P1[0]
( TCK, SWDCK, GPIO)P1[1]
(Configurable XRES , GPIO)P1[2]
( TDO, SWV, GPIO)P1[3]
(TDI, GPIO)P1[4]
(NTRST, GPIO)P1[5]
VDDIO0
P0[3] ( GPIO,OPAMP0-/EXTREF0)
P0[2] ( GPIO, OPAMP 0+/SAR1 EXTREF)
P0[1] ( GPIO, OPAMP
0
OUT )
P0[0] ( GPIO, OPAMP
2
OUT )
P4[1] ( GPIO)
P4[0] ( GPIO)
P12[3] ( SIO)
P12[2] ( SIO)
VSSD
VDDA
VSSA
VCCA
NC
NC
NC
NC
NC
NC
P15[3] ( GPIO, KHZ XTAL:XI)
P15[2] ( GPIO, KHZ XTAL:XO)
P12[1] ( SIO,I2C1 : SDA)
P12[0] ( SIO,I2C1 : SCL)
P3[7] ( GPIO, OPAMP
3
OUT )
P3[6] ( GPIO, OPAMP
1
OUT )
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
Lines show VDDIO
I/O Supply Association
Note
7. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.



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