RT9607 datasheet(11/15 Pages) RICHTEK

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RT9607/A

DS9607/A-07 April 2011

www.richtek.com

Application Information

The RT9607/A has power on protection function which held

UGATE and LGATE low before VCC up cross the rising

threshold voltage. After the initialization, the PWM signal

takes the control. The rising PWM signal first forces the

LGATE signal turns low then UGATE signal is allowed to

go high just after a non-overlapping time to avoid shoot-

through current. The falling of PWM signal first forces

UGATE to go low. When UGATE and PHASE signal reach

a predetermined low level, LGATE signal is allowed to

turn high. The non-overlapping function is also presented

between UGATE and LGATE signal transient.

The PWM signal is recognized as high if above rising

threshold and as low if below falling threshold. Any signal

level in this window is considered as tri-state, which causes

turn-off of both high side and low-side MOSFET. When

PWM input is floating (not connected), internal divider

will pull the PWM to 1.9V to give the controller a

recognizable level. The maximum sink/source capability

of internal PWM reference is 60

μA.

The PVCC pin provides flexibility of both high side and

low side MOSFET gate drive voltages. If 8V, for example,

is applied to PVCC, then high side MOSFET gate drive is

8V to 1.5V (approximately, internal diode plus series

resistance voltage drop). The low side gate drive voltage

is exactly 8V.

The RT9607/A implements a power on over-voltage

protection function. If the PHASE voltage exceeds 1.5V

at power on, the LGATE would be turn on to pull the

PHASE low until the PHASE voltage goes below 1.5V.

Such function can protect the CPU from damage by some

short condition happened before power on, which is

sometimes encountered in the M/B manufacturing line.

Non-overlap Control

To prevent the overlap of the gate drives during the UGATE

turn low and the LGATE turn high, the non-overlap circuit

monitors the voltages at the PHASE node and high side

gate drive (UGATE-PHASE). When the PWM input signal

goes low, UGATE begins to turn low (after propagation

delay). Before LGATE can turn high, the non-overlap

protection circuit ensures that the monitored voltages have

gone below 1.2V. Once the monitored voltages fall below

1.2V, LGATE begins to turn high. For short pulse condtion,

if the PHASE pin had not gone high after LGATE turns

low, the LGATE has to wait for 200ns before turn high

only under short pulse (t

<60ns) condition. By waiting

for the voltages of the PHASE pin and high side gate drive

to fall below 1.2V, the non-overlap protection circuit

ensures that UGATE is low before LGATE turns high. Also

to prevent the overlap of the gate drives during LGATE

turn low and UGATE turn high, the non-overlap circuit

monitors the LGATE voltage. When LGATE go below 1.2V,

UGATE is allowed to go high.

Driving power MOSFETs

The DC input impedance of the power MOSFET is

extremely high. When Vgs at 12V (or 5V), the gate draws

the current only few nanoamperes. Thus once the gate

has been driven up to

“ON”ON level, the current could be

negligible.

However, the capacitance at the gate to source terminal

should be considered. It requires relatively large currents

to drive the gate up and down 12V (or 5V) rapidly. It also

required to switch drain current on and off with the required

speed. The required gate drive currents are calculated as

follows.

Figure1. The gate driver must supply Igs to Cgs and Igd to

Cgd

GND

gs2

gd2

gs2

gd2

gs1

gd1

gs1

+12V

Vg2

Vg1

Vphase

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