PXS30 datasheet(8/139 Pages) FREESCALE

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PXS30 Microcontroller Data Sheet, Rev. 1

Preliminary—Subject to Change Without Notice

Introduction

Freescale Semiconductor

•

Floating point

—IEEE

 754 compatible with software wrapper

— Single precision in hardware; double precision with software library

— Conversion instructions between single precision floating point and fixed point

•

Long cycle time instructions (except for guarded loads) do not increase interrupt latency in the

PXS30

•

To reduce latency, long cycle time instructions are aborted upon interrupt requests

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Extensive system development support through Nexus debug module

1.5.2

Crossbar switch (XBAR)

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32-bit address bus, 64-bit data bus

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Simultaneous accesses from different masters to different slaves (there is no clock penalty when a

parked master accesses a slave)

1.5.3

Memory Protection Unit (MPU)

The Memory Protection Unit splits the physical memory into 16 different regions. Each master (DMA,

FlexRay, CPU) can be assigned different access rights to each region.

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16-region MPU with concurrent checks against each master access

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32-byte granularity for protected address region

1.5.4

Enhanced Direct Memory Access (eDMA) controller

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32 channels support independent 8-, 16-, 32-bit single value or block transfers

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Supports variable-sized queues and circular queues

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Source and destination address registers are independently configured to post-increment or remain

constant

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Each transfer is initiated by a peripheral, CPU, or eDMA channel request

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Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single

value or block transfer

1.5.5

Interrupt Controller (INTC)

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208 peripheral interrupt requests

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8 software settable sources

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Unique 9-bit vector per interrupt source

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16 priority levels with fixed hardware arbitration within priority levels for each interrupt source

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Priority elevation for shared resources

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