PXD20 datasheet(75/130 Pages) FREESCALE

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Electrical characteristics

PXD20 Microcontroller Data Sheet, Rev. 2

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

4.8

DC electrical specifications

4.8.1

DC specification for CMOS090LP2 library @ VDDE = 3.3 V

NOTE

These pad specifications are applicable for pads in the Digital segment Only. See the

“GPIO power bank supplies and functionality” table in the “Voltage Regulators and Power

Supplies” chapter of the reference manual for details.

6 Flash in Low Power. RCOSC 128 kHz and RCOSC 16 MHz ON. 10 MHz XTAL clock. FlexCAN: instances: 0, 1ON (clocked

but no reception or transmission), LINFLEX: instances 0, 1, 2 ON (clocked but no reception or transmission). eMIOS: instance:

0, 1 ON - 16 channels on with PWM20K Hz. DSPI: instance: 0 (clocked but no communication). DCUs, TCON, VIU, GPU clock

gated, RTC/API ON.PIT ON. STM ON. ADC ON but not converting.

7 No clock, RC 16MHz off, RCI 128 kHz on, PLL off, HPvreg off, ULPVreg/LPVreg on. All possible peripherals off and clock

gated. Flash in power down mode.

8 ULPreg ON, HP/LPVreg off, 64 KB RAM on, device configured for minimum consumption, all possible modules switched off.

9 32 KHz oscillator operates at 32,768 Hz.

10 ULPreg ON, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules switched off.

Table 21. DC electrical specifications

Symbol

Parameter

Condition

Value

Unit

SpecID

Min

Max

Vdd

P Core supply voltage

—

1.08

1.47

D9.1

Vdde

P I/O supply voltage

—

3.0

3.6

D9.2

Vdd33

P I/O pre-driver supply voltage

—

3.0

3.6

D9.3

Vih_c

P CMOS input buffer high

voltage

With hysteresis enabled

0.65

 Vdde

Vdde + 0.3

D9.4

With hysteresis disabled

0.55

 Vdde

Vdde + 0.3

Vil_c

P CMOS input buffer low

voltage

With hysteresis enabled

Vss – 0.3

0.35

 Vdde

D9.5

With hysteresis disabled

Vss – 0.3

0.40

 Vdde

Vhys_c

T CMOS input buffer hysteresis

—

0.1

 Vdde

—

D9.6

Vih_fod_h

P 5 V tolerant CMOS input

buffer high voltage

With hysteresis enabled

0.65

 Vdd33 Vdd33 + 0.3

D9.7

Vil_fod_h

P 5 V tolerant CMOS input

buffer low voltage

With hysteresis enabled

Vss – 0.3

0.35

 Vdd33

D9.8

Iact_s

T Selectable weak

pullup/pulldown current

—

150

AD9.9

Iinact_d

P Digital pad input leakage

current

Weak pull inactive

–2.5

2.5

A

D9.10

Iinact_a

P Analog pad input leakage

current

Weak pull inactive

–150

150

A

D9.11

Voh

P Output high voltage

—

0.8

 Vdde

—

D9.12

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