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WM8310 датащи(PDF) 65 Page - Wolfson Microelectronics plc |
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WM8310 датащи(HTML) 65 Page - Wolfson Microelectronics plc |
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65 / 291 page ![]() Pre-Production WM8310 w PP, May 2012, Rev 3.1 65 14.6.4 DCRW PAGE 3 Page 3 of the DCRW occupies register addresses R30744 (7818h) to R30751 (781Fh). This contains user-programmable data. This page of data is normally loaded from OTP when ‘ON’ state transition is scheduled (except in Development Mode or if RECONFIG_AT_ON = 0). This page of data can also be loaded from OTP using the OTP_READ command; it can be written to the OTP using the OTP_WRITE command. This page of data is loaded from the second page of ICE memory (10h to 1Fh) when ‘ON’ state transition is scheduled in Development Mode (if RECONFIG_AT_ON = 1). This page of data can also be loaded from ICE using the ICE Read command. Note that ICE Address 10h corresponds to bits 15:8 at the start address of DCRW Page 3; ICE Address 11h corresponds to bits 7:0 at the same DCRW address. The contents of DCRW Page 3 include the registers listed in Table 31. REGISTER FUNCTION REFERENCE LDO9_ON_SLOT [2:0] LDO Regulator 9 See Section 15.12.4 LDO9_ON_VSEL [4:0] See Section 15.12.4 LDO10_ON_SLOT [2:0] LDO Regulator 10 See Section 15.12.4 LDO10_ON_VSEL [4:0] See Section 15.12.4 LDO11_ON_SLOT [2:0] LDO Regulator 11 See Section 15.12.4 LDO11_ON_VSEL [3:0] See Section 15.12.4 EPE1_ON_SLOT [2:0] External Power Converter Enable See Section 15.12.5 EPE2_ON_SLOT [2:0] See Section 15.12.5 GP1_DIR GPIO1 See Section 21.3 GP1_PULL [1:0] See Section 21.3 GP1_INT_MODE See Section 21.3 GP1_PWR_DOM See Section 21.3 GP1_POL See Section 21.3 GP1_OD See Section 21.3 GP1_ENA See Section 21.3 GP1_FN [3:0] See Section 21.3 GP2_DIR GPIO2 See Section 21.3 GP2_PULL [1:0] See Section 21.3 GP2_INT_MODE See Section 21.3 GP2_PWR_DOM See Section 21.3 GP2_POL See Section 21.3 GP2_OD See Section 21.3 GP2_ENA See Section 21.3 GP2_FN [3:0] See Section 21.3 GP3_DIR GPIO3 See Section 21.3 GP3_PULL [1:0] See Section 21.3 GP3_INT_MODE See Section 21.3 GP3_PWR_DOM See Section 21.3 GP3_POL See Section 21.3 GP3_OD See Section 21.3 GP3_ENA See Section 21.3 GP3_FN [3:0] See Section 21.3 GP4_DIR GPIO4 See Section 21.3 GP4_PULL [1:0] See Section 21.3 GP4_INT_MODE See Section 21.3 GP4_PWR_DOM See Section 21.3 GP4_POL See Section 21.3 GP4_OD See Section 21.3 GP4_ENA See Section 21.3 GP4_FN [3:0] See Section 21.3 |
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