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WM8224 датащи(PDF) 8 Page - Wolfson Microelectronics plc |
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WM8224 датащи(HTML) 8 Page - Wolfson Microelectronics plc |
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8 / 50 page ![]() WM8224 Production Data w PD, Rev 4.1, June 2012 8 Test Conditions AVDD = DVDD = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 60MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Zero-scale transition error Gain = 0dB; PGA[8:0] = 18(hex) 20 mV Differential non-linearity DNL 10-bit 0.5 LSB Integral non-linearity (pk-pk/2) INL 10-bit 7 LSB Channel to channel gain matching 2.5 % Output noise Unity Gain 10-bit (Unused channels grounded) 0.5 LSB rms Programmable Gain Amplifier Resolution 9 bits Gain ] : [ PGA * . . 0 8 511 34 7 66 0 V/V Max gain, each channel GMAX 7.7 V/V Min gain, each channel GMIN 0.65 V/V Analogue to Digital Converter Resolution 10 bits Speed 60 MSPS Full-scale input range (2*(VRT-VRB)) LOWREFS=0 2 V LOWREFS=1 1.2 V Notes: 1. Full-scale input voltage denotes the differential input signal amplitude (VIN-VRLC in non-CDS mode, VIN-RESET level in CDS mode) that can be gained to match the ADC full-scale input range. 2. Input signal limits are the limits within which each input voltage and VRLC reference must lie. |
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