WM8973CLGEFLSLASHV datasheet(45/63 Pages) WOLFSON

45 / 63 page

Production Data

WM8973L

PD, Rev 4.5, December 2011

MASTER MODE ADCLRC AND DACLRC ENABLE

In Master mode, by default ADCLRC is disabled when the ADC is disabled and DACLRC is disabled

when the DAC is disabled. Register bit LRCM, register 24(18h) bit[2] changes the control so that the

ADCLRC and DACLRC are disabled only when ADC and DAC are disabled. This enables the user to

use e.g. ADCLRC for both ADC and DAC LRCLK and disable the ADC when DAC only operation is

required, (see Table 36).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R24(18h)

Additional

Control (2)

LRCM

Selects disable mode for ADCLRC and

DACLRC

0 = ADCLRC disabled when ADC (Left and

Right) disabled, DACLRC disabled when

DAC (Left and Right) disabled.

1 = ADCLRC and DACLRC disabled only when

ADC (Left and Right) and DAC (Left and

Right) are disabled.

Table 36 ADCLRC/DACLRC Enable

BIT CLOCK MODE

The default master mode bit clock generator produces a bit clock frequency based on the sample rate

and input MCLK frequency as shown in Table 40. When enabled by setting the appropriate BCM[1:0]

bits, the bit clock mode (BCM) function overrides the default master mode bit clock generator to

produce the bit clock frequency shown in the table below:

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R8 (08h)

Clocking and

Sample Rate

Control

8:7

BCM[1:0]

BCLK Frequency

00 = BCM function disabled

01 = MCLK/4

10 = MCLK/8

11 = MCLK/16

Table 37 Master Mode BCLK Frequency Control

The BCM mode bit clock generator produces 16 or 24 bit clock cycles per sample. The number of bit

clock cycles per sample in this mode is determined by the word length bits (WL[1:0]) in the Digital

Audio Interface Format register (R7). When these bits are set to 00, there will be 16 bit clock cycles

per sample. When these bits are set to 01, 10 or 11, there will be 24 bit clock cycles per sample.

Please refer to Figure 25.

The BCM generator uses the ADCLRC signal, hence the ADCLRC signal must be enabled when

using bit clock mode. To enable the ADCLRC signal, either the ADC must be powered up or, if the

ADC is not in use, the LRCM bit must be set to enable both the ADCLRC and DACLRC signals when

either the ADC or the DAC is enabled.

When the BCM function is enabled, the following restrictions apply:

1. The bit clock invert (BCLKINV) function is not available.

2. The DAC and ADC must be operated at the same sample rate.

3. DSP late digital audio interface mode is not available and must not be enabled.

Figure 25 Bit Clock Mode

Note: The shaded bit clock cycles are present only when 24-bit mode is selected. Please refer to the

"Bit Clock Mode" description for details.

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