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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8956CGEFL/V датащи(PDF) 65 Page - Wolfson Microelectronics plc |
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WM8956CGEFL/V датащи(HTML) 65 Page - Wolfson Microelectronics plc |
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65 / 80 page  Production Data WM8956 w PD, November 2011, Rev 4.1 65 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO Additional Control (2) 6 HPSWEN 0 Headphone Switch Enable 0 = Headphone switch disabled 1 = Headphone switch enabled Headphone Jack Detect 5 HPSWPOL 0 Headphone Switch Polarity 0 = HPDETECT high = headphone 1 = HPDETECT high = speaker Headphone Jack Detect 4 Reserved 3 TRIS 0 Switches DACLRC and BCLK to inputs. 0 = DACLRC and BCLK are inputs (slave mode) or outputs (master mode) 1 = DACLRC and BCLK are inputs Audio Interface Control 2:0 000 Reserved R25 (19h) Power Mgmt (1) 8:7 VMIDSEL[1:0] 00 Vmid Divider Enable and Select 00 = Vmid disabled (for OFF mode) 01 = 2 x 50k divider enabled (for playback / record) 10 = 2 x 250k divider enabled (for low-power standby) 11 = 2 x 5k divider enabled (for fast start-up) Power Management 6 VREF 0 VREF (necessary for all other functions) 0 = Power down 1 = Power up Power Management 5 AINL 0 Analogue in PGA Left 0 = Power down 1 = Power up Power Management 4 AINR 0 Analogue in PGA Right 0 = Power down 1 = Power up Power Management 3:2 00 Reserved 1 MICB 0 MICBIAS 0 = Power down 1 = Power up Power Management 0 DIGENB 0 Master Clock Disable 0 = Master clock enabled 1 = Master clock disabled Power Management R26 (1Ah) Power Mgmt (2) 8 DACL 0 DAC Left 0 = Power down 1 = Power up Power Management 7 DACR 0 DAC Right 0 = Power down 1 = Power up Power Management 6 LOUT1 0 LOUT1 Output Buffer 0 = Power down 1 = Power up Power Management 5 ROUT1 0 ROUT1 Output Buffer 0 = Power down 1 = Power up Power Management 4 SPKL 0 SPK_LP/SPK_LN Output Buffers 0 = Power down 1 = Power up Power Management 3 SPKR 0 SPK_RP/SPK_RN Output Buffers 0 = Power down 1 = Power up Power Management 2 0 Reserved |
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