WM8533 datasheet(24/41 Pages) WOLFSON

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WM8533

Production Data

PD, July 2012, Rev 4.0

DAC FEATURES

SYSTEM ENABLE

The WM8533 includes a number of enable and disable mechanisms to allow the device to be

powered on and off in a pop-free manner. The SYS_ENA [1:0] control bits enable the DAC and

analogue paths.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R2 (02h)

PSCTRL1

1:0

SYS_ENA

[1:0]

System Power Control

00 = Off

01 = Power down

10 = Power up (Digital Soft Mute)

11 = Power up (un-muted)

Table 12 System Enable Control

Note: MCLK must be present at all times when using the SYS_ENA [1:0] bits. If MCLK is stopped at

any point the device will power down to the ‘off’ state, but all register settings will remain. Restarting

MCLK will start the device internal power sequence and the device will return to the power state set

by the SYS_ENA [1:0] bits.

The power up and power down sequences are summarised in Figure 22. There is no requirement to

manually cycle the device through the sequence via register writes, as the device will always

automatically step through each stage in the sequence.

Power Up

When SYS_ENA [1:0]=00, the internal clocks are stopped and all analogue and digital blocks are

disabled for maximum power saving. The device starts up in this state in software mode. Setting

SYS_ENA [1:0]=01 enables the internal charge pump and required control circuitry, but the signal

path remains powered down. When SYS_ENA [1:0]=10 all blocks are powered up sequentially and

full system configuration is achieved. Once this is complete, the device is ready to pass audio but is

muted with a digital soft mute. Setting SYS_ENA [1:0]=11 releases the digital soft mute and audio

playback begins.

Power Down

When SYS_ENA [1:0]=11 the device is powered up and passing audio.

Changing SYS_ENA

[1:0]=10 applies a digital soft mute to the output, with attenuation of 100dB on the input signal.

Setting SYS_ENA [1:0]=01 sequentially powers down all circuit blocks but leaves the charge pump

and required control circuitry enabled. This state is equivalent to the Hardware Mode mute state, and

will give 120dB attenuation on the input signal. This can be considered the low-power standby state.

Finally, setting SYS_ENA [1:0]=00 will disable all circuit blocks including the charge pump, and full

system initialisation will be required to restart the device.

Figure 22 SYS_ENA [1:0] Power Up and Down Sequences

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