поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

WM8533 датащи(PDF) 21 Page - Wolfson Microelectronics plc

номер детали WM8533
подробное описание детали  24-bit 192kHz Stereo DAC with 2Vrms Ground Referenced Line Output
PDF  41 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  WOLFSON [Wolfson Microelectronics plc]
домашняя страница  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8533 датащи(HTML) 21 Page - Wolfson Microelectronics plc

Back Button WM8533 Datasheet HTML 17Page - Wolfson Microelectronics plc WM8533 Datasheet HTML 18Page - Wolfson Microelectronics plc WM8533 Datasheet HTML 19Page - Wolfson Microelectronics plc WM8533 Datasheet HTML 20Page - Wolfson Microelectronics plc WM8533 Datasheet HTML 21Page - Wolfson Microelectronics plc WM8533 Datasheet HTML 22Page - Wolfson Microelectronics plc WM8533 Datasheet HTML 23Page - Wolfson Microelectronics plc WM8533 Datasheet HTML 24Page - Wolfson Microelectronics plc WM8533 Datasheet HTML 25Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 41 page
background image
Production Data
WM8533
w
PD, July 2012, Rev 4.0
21
Figure 19 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Master)
Figure 20 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave)
Figure 21 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Slave)
DIGITAL AUDIO INTERFACE CONTROL
The control of the audio interface in software mode is achieved by register write. Dynamically
changing the audio data format may cause erroneous operation and is not recommended.
Digital audio data is transferred to the WM8533 via the digital audio interface. The DAC operates in
master or slave mode.
The DAC audio interface requires left/right frame clock (LRCLK) and bit clock (BCLK). These can be
supplied externally (slave mode) or they can be generated internally (master mode). Selection of
master and slave mode is achieved by setting AIF_MSTR bit in Register 3.
The frequency of LRCLK in master mode is dependent upon the DAC master clock frequency and the
AIF_SR [2:0] bits. The frequency of BCLK in master mode can be selected by AIF_BCLKDIV [2:0].
In slave mode, the MCLK to LRCLK ratio can be auto-detected or set manually using the AIF_SR
[2:0] bits.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com