SPEAR1340 datasheet(199/200 Pages) STMICROELECTRONICS

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SPEAr1340

Revision history

Doc ID 023063 Rev 4

199/200

03-Aug-2012

2 (cont’d)

Updated Section 4.4.1: 3V3/2V5/1V8 I/O buffers

(IOTYPE1/IOTYPE2/IOTYPE3) and Section 4.4.2: IOTYPE4 I/O

buffers.

Updated Section 4.5: Voltage regulator characteristics.

Inserted Section 4.7: Required external components (moved from

Pin description chapter).

Added Section 4.6: MiPHY characteristics

Updated Section 4.10: Reset release:

– Updated the introduction.

– Renamed and updated Figure 14: Cold reset release.

– Added new Figure 15: Warm reset release.

Chapter 5: Timing characteristics

– Added new Section 5.1: Reset timing characteristics.

– Updated the entire chapter (timing waveforms and tables for each

IP) with new timing information.

– Removed RGMII information (see SPEAr1340 Errata sheet for

more information).

11-Oct-2012

Updated Section 2.29: Cryptographic co-processor (C3)

Added infomation on compensation cells Table 2:

Headers/abbreviations

Added I/O compensation cell column to table Table 3: Ball

characteristics

Updated Table 59: Reset timing characteristics

Updated Section 5.7: GMAC timing characteristics

Corrected Figure 34: MCIF - SD/SDIO/MMC mode timing waveform

Updated t2i in Table 88: MCIF - CF true IDE PIO mode timing

characteristics

Updated SSP Figure 42, Table 100 added Table 95

Updated TD3 in Figure 43 and Figure 44

Updated notes below tables in Section 5.9: I2C timing characteristics

Corrected Table 41: SMI timing waveform

Updated Section 5.16: UART timing characteristics

26-10-2012

Updated Figure 15: Warm reset release on page 149

Updated Table 100: SSP timing characteristics (slave mode)

Table 109.

Document revision history (continued)

Date

Revision

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