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SPEAR1340 датащи(PDF) 163 Page - STMicroelectronics

номер детали SPEAR1340
подробное описание детали  Dual-core Cortex A9 HMI embedded MPU
PDF  200 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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SPEAR1340 датащи(HTML) 163 Page - STMicroelectronics

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SPEAr1340
Timing characteristics
Doc ID 023063 Rev 4
163/200
The hold constraint, vice versa, is fixed:
THCLK - TW + TD ≥ THOLD (SRAM)
When reading a data, since the FSMC strobes it 1 HCLK cycle before the rising edge of
FSMC_REn, the user should choose the correct value of Data_ST in order to satisfy the
following setup constraint:
TDATA_ST - TMEM - TDEL ≥ TSETUP (FSMC_FFs)
TDEL is the sum of 2 internal delays of SPEAr:
●
From the FSMC flops to the FSMC_REn pad;
●
From the FSMC_IO pads to the FSMC flops.
Table 70.
Timings for 8-/16-bit SRAM configuration on FSMC_CE0n
Symbol
Min
Max
Unit
TAD
-2.19
4.33
ns
TBL (16-bit)
-2.79
4.80
TD (8-bit)
-2.78
6.40
TD (16-bit)
-3.02
6.40
TW
-1.66
1.99
TR
-1.41
2.27
Table 71.
Timings for 8-/16-bit SRAM configuration on FSMC_CE1n
Symbol
Min
Max
Unit
TAD
-1.82
4.60
ns
TBL (16-bit)
-2.43
5.08
TD (8-bit)
-2.41
6.67
TD (16-bit)
-2.65
6.67
TW
-1.30
2.27
TR
-1.08
2.55
Table 72.
Internal delays for 8-/16-bit SRAM configuration
Symbol
Min
Max
Unit
TDEL (8-bit)
4.03
16.25
ns
TDEL (16-bit)
4.01
16.54
TSETUP (FSMC_FFs)
0.05
0.46



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