SPEAR1340 datasheet(160/200 Pages) STMICROELECTRONICS

160 / 200 page

Timing characteristics

SPEAr1340

160/200

Doc ID 023063 Rev 4

TAD, TAV, TD, TW, TR and TSTROBE are fixed values: they depend only on the internal timings

of SPEAr.

TADDR_ST, THOLD_ADDR, TDATA_ST and TOEN_DLY are programmable timings defined by

FSMC registers. They can be calculated as:

TADDR_ST = (Addr_ST + 1) * THCLK (min value for Addr_ST is 0)

THOLD_ADDR = (Hold_addr + 1) * THCLK (min value for Hold_addr is 0)

TDATA_ST = Data_ST * THCLK (min value for Data_ST is 0 for Read and 1 for Write)

TOEN_DLY = OEn_delay * THCLK (when 1, the output enable rises 1 HCLK cycle before

the chip select)

Since the data strobe always happens 1 HCLK cycle before the rising edge of the chip

select, TSTROBE can be calculated as:

TSTROBE = THCLK - TW

THCLK = 6 ns (period of the AHB clock, the FSMC input clock)

TMEM is the output delay of the NOR Flash.

The FSCM_REn signal can toggle either after the de-assertion of the chip select

(Extended_Mode = 0) or after the Addr_ST phase (Extended_Mode = 1).

In the 1st case the programmable timings for Read and Write are unique while in the 2nd

case they can be different from each other.

When writing a data, since the NOR strobes it on the rising edge of FSMC_WEn, the user

should choose the correct values of Data_ST (and eventually Hold_addr) in order to satisfy

the setup constraint:

THCLK + TW (+ THOLD_ADDR) + TDATA_ST - TD ≥ TSETUP (NOR_FLASH)

The hold constraint, vice versa, is fixed:

THCLK - TW + TD ≥ THOLD (NOR_FLASH)

When reading a data, since the FSMC strobes it 1 HCLK cycle before the rising edge of

FSMC_REn, the user should choose the correct value of Data_ST in order to satisfy the

following setup constraint:

TDATA_ST - TMEM - TDEL ≥ TSETUP (FSMC_FFs)

TDEL is the sum of 2 internal delays of SPEAr:

●

From the FSMC flops to the FSMC_REn pad;

●

From the FSMC_IO pads to the FSMC flops.

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