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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPEAR1340 датащи(PDF) 158 Page - STMicroelectronics |
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SPEAR1340 датащи(HTML) 158 Page - STMicroelectronics |
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158 / 200 page  Timing characteristics SPEAr1340 158/200 Doc ID 023063 Rev 4 When reading a data, since the FSMC strobes it 1 HCLK cycle before the rising edge of FSMC_REn, the user should choose the correct value of Data_ST in order to satisfy the following setup constraint: TWAIT - TMEM - TDEL ≥ TSETUP (FSMC_FFs) TDEL is the sum of 2 internal delays of SPEAr: ● From the FSMC flops to the FSMC_REn pad; ● From the FSMC_IO pads to the FSMC flops. Table 64. Timings for 8-/16-bit NAND Flash configuration on FSMC_CE0n Symbol Min Max Unit TALE -1.47 2.44 ns TCLE -1.77 1.83 TD (8-bit) -2.76 6.48 TD (16-bit) -2.82 6.48 TW -1.56 2.21 TR -1.29 2.50 Table 65. Timings for 8-/16-bit NAND Flash configuration on FSMC_CE1n Symbol Min Max Unit TALE -1.44 2.41 ns TCLE -1.76 1.80 TD (8-bit) -2.75 6.45 TD (16-bit) -2.81 6.45 TW -1.50 2.18 TR -1.23 2.47 Table 66. Internal delays for 8-/16-bit NAND Flash configuration Symbol Min Max Unit TDEL (8-bit) 3.82 16.34 ns TDEL (16-bit) 3.82 16.63 TSETUP (FSMC_FFs) 0.06 0.49 |
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