STA321MPL datasheet(24/50 Pages) STMICROELECTRONICS

24 / 50 page

Registers

STA321MP

24/50

Doc ID 022647 Rev 1

7.2.3

Configuration register E (0x04)

Each individual channel output can be set to output a binary PWM stream. In this mode

output A of a channel will be considered the positive output and output B is the negative

inverse.

7.2.4

Configuration register F (0x05)

The STA321MP features an internal digital high-pass filter for the purpose of AC coupling.

The purpose of this filter is to prevent DC signals from passing through an FFX amplifier. DC

signals can cause speaker damage.

If HPB = 1, then the filter that the high-pass filter utilizes is made available as user-

programmable biquad#1.

Both limiters can be used in one of two ways, anti-clipping or dynamic range compression.

When used in anti-clipping mode, the limiter threshold values are constant and dependent

on the limiter settings.

C8BO

C7BO

C6BO

C5BO

C4BO

C3BO

C2BO

C1BO

Bit

RST

Name

Description

0RW

C1BO

Channels 1, 2, 3, 4, 5, 6, 7, and 8 binary output

mode enable bits. A setting of 0 indicates ordinary

FFX tristate output. A setting of 1 indicates binary

output mode.

1RW

C2BO

2RW

C3BO

3RW

C4BO

4RW

C5BO

5RW

C6BO

6RW

C7BO

7RW

C8BO

PWMS2

PWMS1

PWMS0

BQL

PSL

DEMP

DRC

HPB

Bit

RST

Name

Description

0RW

HPB

High-pass filter bypass bit: a setting of 1 bypasses

the internal AC coupling digital high-pass filter

Bit

RST

Name

Description

DRC

Dynamic range compression/anti-clipping

0: limiters act in anti-clipping mode

1: limiters act in dynamic range compression mode

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