STA321MPL datasheet(21/50 Pages) STMICROELECTRONICS

21 / 50 page

STA321MP

Registers

Doc ID 022647 Rev 1

21/50

7.2

7.2.1

Configuration register A (0x00)

The STA321MP supports a sampling rate of 2.8224 MHz. Therefore the internal clock is:

●

90.3168 MHz for the respective sampling frequency

The external clock frequency provided to the XTI pin must be a multiple of the input

sampling frequency (fs). The relationship between the input clock and the input sampling

rate is determined by both the MCSn and the IRn (input rate) register bits. The MCSn bits

determine the PLL factor generating the internal clock and the IRn bits determine the

oversampling ratio used internally.

Interpolation ratio select

The STA321MP has variable interpolation (oversampling) settings such that internal

processing and FFX output rates remain consistent. The first processing block interpolates

by either 4 times, 2 times, or 1 time (pass-through).

The oversampling ratio of this interpolation is determined by the IR bits.

COS1

COS0

DSPB

IR1

IR0

MCS2

MCS1

MCS0

Bit

RST

Name

Description

0RW

MCS0

Master clock select: selects the ratio between the

input sampling frequency (PDM I/FCLK) and the

input clock(XTI).

1RW

MCS1

2RW

MCS2

Input sampling rate

fs (kHz)

MCS[2:0]

1XX

011

010

001

000

PDM I/F 2822.4

2 * fs

4 * fs

6 * fs

8 * fs

10 * fs

Bit

RST

Name

Description

IR0

Interpolation ratio select: selects the internal

interpolation ratio based on the input sampling

frequency

4RW

IR1

IR[1,0]

Input sampling rate

Fs (kHz)

1st stage interpolation ratio

2822.4

PDM CLK to 176.4 kHz conversion

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