STULPI01A_12 datasheet(32/44 Pages) STMICROELECTRONICS

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ULPI registers

STULPI01A, STULPI01B

32/44

Doc ID 14817 Rev 4

Note:

04h-06h(Read), 04h(Write), 05h(Set), 06h(Clear). These addresses control UTMI function

setting of the USB transceiver PHY.

Table 17.

Function control register

Field name

Bits

Access

Reset

Description

XcvrSelect

1:0

rd/wr/s/c

01b

Selects the required transceiver speed.

00b: enables HS transceiver

01b: enables FS transceiver

10b: enables LS transceiver

11b: enables FS transceiver for LS packets (FS preamble

is automatically pre-pended)

Important note: Every time XcvrSelect is changed to

‘00’, the output ULPI clock is stopped for the time needed

for internal DLL calibration.

TermSelect

rd/wr/s/c

Controls the internal pull-up resistors or HS terminations.

Control over these resistors changes depending on

XcvrSelect, OpMode, DpPulldown and DmPulldown, as

shown in Table 24.

OpMode

4:3

rd/wr/s/c

00b

Selects the required bit encoding style during transmit.

00b: normal operation

01b: non-driving

10b: disables bit-stuff and NRZI encoding

11b: does not automatically add SYNC and EOP when

transmitting. Must be used only for HS packets.

Reset

rd/wr/s/c

Active high transceiver reset. After the link sets this bit,

the STULPI01 asserts DIR and reset the UTMI+ core.

When the reset is complete, the STULPI01 de-asserts

DIR and automatically clears this bit. After de-asserting

DIR, the STULPI01 re-asserts DIR and sends an RX

CMD update to the link.

Note: If Reset bit is set to ‘1’ and SuspendM bit is set to

‘0’ in the same register access, SuspendM bit takes

higher priority and the chip enters Low-power mode.

Reset bit is cleared.

SuspendM

rd/wr/s/c

Active low PHY suspend. Puts PHY into Low-power

mode. The STULPI01 automatically sets this bit to ‘1’

when Low-power mode is exited.

0b: Low-power mode

1b: Powered

Note: If Reset bit is set to ‘1’ and SuspendM bit is set to

‘0’ in the same register access, SuspendM bit takes

higher priority and the chip enters Low-power mode.

Reset bit is cleared.

Reserved

rd/wr/s/c

Reserved

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