SC5014AEVB datasheet(22/27 Pages) SEMTECH

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SC5014A

acknowledges and the master terminates the transfer with

the stop condition [P].

(2) Combined Format — Read

After the start condition [S], the slave address is sent, fol-

lowed by an eighth bit indicating a write. The SC504A I2C

then acknowledges that it is being addressed, and the

master responds with an 8-bit data byte consisting of the

sends the repeated start condition [Sr]. Once again, the

slave address is sent, followed by an eighth bit indicating

a read. The slave responds with an acknowledge and the

8-bit data from the previously addressed register; the

master then sends a non-acknowledge (NACK). Finally, the

master terminates the transfer with the stop condition [P].

(3) Stop Separated Reads

Stop-separated reads can also be used. This format allows

a master to set up the register address pointer for a read

and return to that slave at a later time to read the data. In

this format the slave address followed by a write command

are sent after a start [S] condition. The SC504A then

acknowledges it is being addressed, and the master

responds with the 8-bit register address. The master sends

a stop or restart condition and may then address another

slave. After performing other tasks, the master can send a

start or restart condition to the SC504A with a read

command. The device acknowledges this request and

returns the data from the register location that had

previously been set up.

Serial Interface

The I2C General Specification

The SC504A is a read-write slave-mode I2C device and

complies with the NXP B.V. I2C standard Version 2., dated

January 2000. The SC504A has user-accessible internal

8-bit registers. The I2C interface has been designed for

program flexibility, supporting direct format for write

operation. Read operations are supported on both com-

bined format and stop separated format. While there is no

auto increment/decrement capability in the SC504A I2C

logic, a tight software loop can be designed to randomly

access the next register independent of which register

you begin accessing. The start and stop commands frame

the data-packet and the repeat start condition is allowed

if necessary.

Limitations to the I2C Specifications

The SC504A only recognizes 7-bit addressing. This means

that 0-bit addressing and CBUS communication are not

compatible. The device can operate in either standard

mode (00kbit/s) or fast mode (400kbit/s).

Slave Address Assignment

The 7-bit slave address is 00 x. The eighth bit is the

data direction bit. 0x5F is used for read operation and

0x5E is used for write operation.

Supported Formats

The supported formats are described in the following

subsections.

(1) Direct Format — Write

The simplest format for an I2C write is direct format. After

the start condition [S], the slave address is sent, followed

by an eighth bit indicating a write. The SC504A I2C then

acknowledges that it is being addressed, and the master

responds with an 8-bit data byte consisting of the register

address. The slave acknowledges and the master sends

the appropriate 8-bit data byte. Once again, the slave

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