2–1

2

Functional Description

2.1

Device Functions

The functions of the TLC320AD56C are described in the following sections.

2.1.1

Operating Frequencies

The sampling (conversion) frequency is derived from the master clock (MCLK) input by equation 1.

fs + Sampling (conversion) frequency +

MCLK

512

(1)

The inverse is the time between the falling edges of two successive primary frame synchronization signals

and is the conversion period.

2.1.2

ADC Signal Channel

To produce excellent common-mode rejection of unwanted signals, the analog signal is processed

differentially until it is converted to digital data.

The input signal is filtered and applied to the ADC input. The ADC converts the signal into discrete output

digital words in 2s-complement format, corresponding to the analog signal value at the sampling time. These

16-bit digital words, representing sampled values of the analog input signal, are clocked out of the serial port

during the frame-sync interval, (DOUT), one word for each primary communication interval. During

secondary communications, the data previously programmed into the registers can be read out with the

appropriate register address, and the read bit set to 1. When no register read is requested, all 16 bits are

0 in the secondary word.

2.1.3

DAC Signal Channel

DIN receives the 16-bit serial data word (2’s complement) from the host during the primary communications

interval and latches the data on the seventeenth rising edge of SCLK. The data are converted to an analog

current by the sigma-delta DAC comprised of a digital interpolation filter, and a digital 1-bit modulator. The

DACs differential outputs OUTP and OUTM are a current output-type, (which requires resistive loading 5k

Ω

maximum). These outputs are then connected to the external low pass filter, as shown in the application

schematics in Figure 3–7 and Figure 3–8 to complete the signal reconstruction. This filter can be

incorporated in the data access arrangement (DAA) for modem applications.

2.1.4

Serial Interface

The digital serial interface consists of the shift clock, the frame synchronization signal, the ADC-channel

data output, and the DAC-channel data input. During the primary 16-bit frame synchronization interval, the

SCLK transfers the ADC channel results from DOUT and transfers 16-bit DAC data into DIN.

During the secondary frame synchronization interval, the SCLK transfers the register read data from DOUT

when the read bit is set to a 1. In addition, the SCLK transfers control and device parameter information into

DIN. The functional sequence is shown in Figure 3–1.

2.1.5

Register Programming

All register programming occurs during secondary communications, and data is latched and valid on the

rising edge of the frame-sync signal. When the default value for a particular register is desired, that register

does not need to be addressed during the secondary communications. The no-op command addresses the

pseudo-register (register 0), and no register programming takes place during this communications.