TLC320AD56 datasheet(13/42 Pages) TI1

13 / 42 page

1–7

Frame Sync and

Sampling Period

The time between the falling edges of successive primary frame-sync signals.

The sampling frequency that is the reciprocal of the sampling period.

Frame-Sync Interval

The time period occupied by 16 shift clocks. It goes high on the sixteenth rising

edge of SCLK after the falling edge of the frame sync.

ADC Channel

This term refers to all signal processing circuits between the analog input and the

digital conversion results at DOUT.

DAC Channel

This term refers to all signal processing circuits between the digital data word

applied to DIN and the differential output analog signal available at OUTP and

OUTM.

Host

Any processing system that interfaces to DIN, DOUT, SCLK, or FS.

Dxx

Bit position in the primary data word (xx is the bit number).

DSxx

Bit position in the secondary data word (xx is the bit number).

The alpha character d represents valid programmed or default data in the control

discussing other data bit portions of the register.

The alpha character X represents a do-not-care bit position within the control

FIR

Finite duration impulse response.

1.7

There are three data and control registers that are used as follows:

The No-Op register. The 0 address allows secondary requests without altering any other

The Control 1 register. The data in this register controls:

•

The software reset

•

The software power down

•

Selection of the normal or auxiliary analog inputs

•

Selection of the digital loopback

•

16-bit or 15-bit mode of operation

•

Selection of monitor amp output

The Control 2 register. The data in this register:

•

Contains the output flag indicating a decimator FIR filter overflow

•

Contains Flag 0 and Flag 1 output values for use in the phone mode

•

Selects the phone mode

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