SLOU330 datasheet(11/18 Pages) TI1

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VCXO

AFE722x

TSW3100

Ext

Ref In

CDCE72010

6x Fs

737.28MHz

92.16 MHz

122.88 MHz

E.g. 10 MHZ or

122.88 MHz

CDCE72010

VCXO

AFE722x

SMA

Connector

CLK IN

CLK INP

CLK INN

CLK IN\

R161

R112

C56

DNI

SMA

Connector

R74

R78

R82

R79

DNI

R76

DNI

AUX IN

CDCE72010

AFE722x

TSW3100

Opt. BPF

www.ti.com

Clocking Configuration

6.2

System Level

In this system configuration on the EVM a VCXO at 6x the

desired clock frequency is required

– alternatively a

different VCXO frequency can be used and the internal

CDCE72010 dividers adjusted accordingly. An external

reference can be locked to the VCXO for coherency using

the CDCE72010. In this configuration the CDCE72010

provides a /6 copy of the VCXO to the AFE722x clock

input as well as a /8 copy to the TSW3100.

Also the AFE722x EVM offers a placeholder for a surface

mount bandpass filter between CDCE72010 and

AFE722x to limit the clock phase noise.

6.3

RX Only

When testing only the ADCs for maximum performance,

the EVM provides an option to connect an external clock

directly to the AFE bypassing the CDCE72010. R74, R76

and R112 need to be modified from their default

configuration.

The DACs of the AFE can still be operated however the

TSW3100 can

’t be used for data generation as no

feedback clock is provided to it.

This option provides the lowest possible jitter option when

combined with an external bandpass filter.

6.4

RX and TX Independent Clocking

The AFE722x supports an option to run the dual ADCs at

a different sampling rate than the dual DACs. With a few

resistor changes, the clocking circuitry on the AFE722x

EVM can be configured to support that feature. However

in this scenario the CDCE72010 is bypassed and no clock

is routed back to the TSW3100. Hence an additional clock

needs to be provided and the CDCE72010 configured

with the appropriate output divider to match the AFE722x

DAC clock rate with the data rate from the TSW3100 (see

6.1

& 6.2).

6.5

Interpolation on the DAC

The AFE722x offers 2x and 4x interpolation of the DAC

output data. In order to employ interpolation on the DAC,

the clock going to the TSW3100 needs to be divided

accordingly. For example interpolation by 2x in the DAC

requires that the data coming from the TSW3100 arrives

½ of the AFE722x clock frequency.

SLOU330

– December 2011

EVM Description

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