Select AFE722x

for ADC

Perform FFT

capture

Enter ADC

sampling rate

Enter desired

input frequency

DCLK

Data

Initial EVM Setup and Basic Test Procedure

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4.3

TX Path Using TSW3100

First the AFE722x digital interface needs to be configured to match the serial LVDS interface from the

TSW3100.

The following control registers need to be set in the

‘General Setup’ tab of the AFE722x programming

software. Also the USB communication warning sign should be monitored after the USB reset to ensure

proper communication with the AFE722x EVM.

Table 1. Control Registers

Register Bit

Setting

Interface

Serial LVDS

Master Override

Enabled

Serial LVDS

2 Wire

Data Orientation

MSB first

Format

2s Complement

Clock Delay

Enabled

Clock Delay

300ps

Frame Clock Delay

Disabled

Frame Clock Delay

0ps

The data coming from the TSW3100 is edge aligned while the AFE722x expects the serial LVDS data to

arrive edge centered. Here the programmable clock delay inside the AFE722x can be used to delay the

edge aligned clock closer towards the center of the data.

The table below shows clock delays for listed DAC sampling rates that showed proper operation.

6

EVM Description

SLOU330

– December 2011

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