SST58SD024 datasheet(13/40 Pages) SST

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Data Sheet

ATA-Disk Chip

SST58SD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192

SST58LD008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192

S71167-05-000

9/01

391

2.3.7 I/O Output (Write) Timing Specification

Note: All times are in nanoseconds. The maximum load on IOCS16 is 1 LSTTL with 50pF total load.

All AC specifications are guaranteed by design.

FIGURE

2-3: I/O WRITE TIMING DIAGRAM

FIGURE

2-4: AC INPUT/OUTPUT REFERENCE WAVEFORMS

TABLE

2-7: I/O WRITE TIMING

Item

Symbol

IEEE Symbol

Min

Max

Data Setup before IOWR#

tsu(IOWR)

tDVIWH

Data Hold following IOWR#

th(IOWR)

tlWHDX

IOWR# Width Time

tw(IOWR)

tlWLIWH

Address Setup before IOWR#

tsuA(IOWR)

tAVIWL

Address Hold following IOWR#

thA(IOWR)

tlWHAX

IOCS16 Delay Falling from Address

tdfIOCS16(ADR)

tAVISL

IOCS16 Delay Rising from Address

tdrIOCS16(ADR)

tAVISH

T2-7.4 391

391 ILL2-8.2

tdrIOCS16(ADR)

tdfIOCS16(ADR)

thA(IOWR)

th(IOWR)

tsu(IOWR)

Din Valid

tsuA(IOWR)

tw(IOWR)

Valid Address1

IOWR#

IOCS16#

D15-D0

1. Valid Address consists of signals CS1FX#, CS3FX# and A2-A0.

391 ILL F11.0

REFERENCE POINTS

OUTPUT

INPUT

VHT

VLT

VHT

VLT

VIHT

VILT

AC test inputs are driven at VIHT (2.4V) for a logic “1” and VILT (0.4V) for a logic “0”. Measurement reference points for

inputs and outputs are VHT (2.0V) and VLT (0.8V). Input rise and fall times (10%

↔ 90%) are <10 ns.

Note: VHT - VHIGH Test

VLT - VLOW Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

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