SST48CF008 datasheet(36/60 Pages) SST

36 / 60 page

Data Sheet

CompactFlash Card

SST48CF008 / 016 / 024 / 032 / 048 / 064 / 096 / 128 / 192 / 256

S71125-03-000

9/01

375

3.1.5.9 Status & Alternate Status Registers (Address 1F7H[177H]&3F6H[376H]; Offsets 7 & E)

These registers return the CompactFlash card status when read by the host. Reading the Status register does

clear a pending interrupt while reading the Auxiliary Status register does not. The meaning of the status bits are

described as follows:

Bit 7 (BUSY) The busy bit is set when the CompactFlash card has access to the command buffer and

registers and the host is locked out from accessing the command register and buffer. No

other bits in this register are valid when this bit is set to a 1.

Bit 6 (RDY)

RDY indicates whether the device is capable of performing CompactFlash card

operations. This bit is cleared at power up and remains cleared until the CompactFlash

card is ready to accept a command.

Bit 5 (DWF)

This bit, if set, indicates a write fault has occurred.

Bit 4 (DSC)

This bit is set when the CompactFlash card is ready.

Bit 3 (DRQ)

The Data Request is set when the CompactFlash card requires that information be

transferred either to or from the host through the Data register.

Bit 2 (CORR) This bit is set when a Correctable data error has been encountered and the data has

been corrected. This condition does not terminate a multi-sector read operation.

Bit 1 (IDX)

This bit is always set to 0.

Bit 0 (ERR)

This bit is set when the previous command has ended in some type of error. The bits in

the Error register contain additional information describing the error. It is recommended

that media access commands such as Read Sectors and Write Sectors) that end with an

error condition should have the address of the first sector in error in the command block

registers.

3.1.5.10 Device Control Register (Address - 3F6H[376H]; Offset E)

This register is used to control the CompactFlash card interrupt request and to issue an ATA soft reset to the card.

This register can be written even if the device is BUSY. The bits are defined as follows:

Bit 7

This bit is an X (don’t care).

Bit 6

This bit is an X (don’t care).

Bit 5

This bit is an X (don’t care).

Bit 4

This bit is an X (don’t care).

Bit 3

This bit is ignored by the CompactFlash card.

Bit 2 (SW Rst) This bit is set to 1 in order to force the CompactFlash card to perform an AT Disk

controller Soft Reset operation. This does not change the PCMCIA Card Configuration

Registers (4.3.2 to 4.3.5) as a hardware Reset does. The Card remains in Reset until

this bit is reset to ‘0.’

Bit1(-IEn)

The Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts

from the CompactFlash card are disabled. This bit also controls the Int bit in the

Configuration and Status Register. This bit is set to 0 at power on and Reset.

Bit0

This bit is ignored by the CompactFlash card.

BUSY

RDY

DWF

DSC

DRQ

CORR

ERR

XXX

SW Rst

-IEn

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