00FFFFh

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0000FFh

1FFFFFh

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1F00FFh

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Block 31(64KB)

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00FFFFh

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0000FFh

1FFFFFh

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1F00FFh

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DLPR100

www.ti.com

DLPS020 – DECEMBER 2009

Figure 1. Memory Blocks of the DLPR100

Functional Description

The memory blocks of the DLPR100 are shown in Figure 1.

SPI Operation

The DLPR100 is accessed through an SPI compatible bus. Data input on the DIO pin is sampled on the rising

edge of the CLK. Data on the DO and DIO pins are clocked out on the falling edge of the CLK.

Write Protection

Upon power-up or at power-down the DLPR100 will maintain a reset condition while VCC is below the threshold

value of VWI. While reset, all operations are disabled and no instructions are recognized. During power-up and

after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time of

tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write

Status Register instructions. Note that the chip select pin (CS) must track the VCC supply level at power-up until

the VCC-min level and tVSL time delay is reached. If needed a pull-up resistor on CScan be used to accomplish

this. After power-up the device is automatically placed in a write-disabled state with the Status Register Write

Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a write operation will be

accepted. After completing a write operation the Write Enable Latch (WEL) is automatically cleared to a

write-disabled status of 0. Software controlled write protection is facilitated using the Write Status Register

instruction and setting the Status Register Protect (SRP) and Block Protect (TB, BP2, BP1, and BP0) bits.

Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored

except for the Released Power-down instruction.

Control and Status Registers

The Read Status Register instruction can be used to provide status on the availability of the Flash memory array,

if the device is write enabled/disabled, and the state of write protect. The Write Status Resister instruction can be

used to configure the device’s write protection feature.

Copyright © 2009, Texas Instruments Incorporated

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