MMA8653FC datasheet(17/56 Pages) FREESCALE

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MMA8653FC

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Freescale Semiconductor, Inc.

•

The MMA8653FC features an interrupt signal that indicates when a new set of measured acceleration data is available, thus

simplifying data synchronization in the digital system that uses the device.

•

The MMA8653FC may also be configured to generate other interrupt signals accordingly, to the programmable embedded

functions of the device for Motion, Freefall, and Orientation.

5.8

Serial I2C interface

Acceleration data may be accessed through an I2C interface, thus making the device particularly suitable for direct interfacing to

a microcontroller. The acceleration data and configuration registers embedded inside the MMA8653FC are accessed through the

I2C serial interface (Table 10, “Serial Interface pins").

•

To enable the I2C interface, VDDIO line must be tied high (i.e., to the interface supply voltage). If VDD is not present and

VDDIO is present, then the MMA8653FC is in OFF mode—and communications on the I2C interface are ignored.

•The I2C interface may be used for communications between other I2C devices; the MMA8653FC does not affect the I2C

bus.

The I2C interface is compliant with Fast mode (400 kHz), and Normal mode (100 kHz) I2C standards (Table 6, “I2C slave timing

values").

I2C operation:

The transaction on the bus is started through a start condition (START) signal. A START condition is defined as a high-to-

low transition on the data line while the SCL line is held high. After START has been transmitted by the Master, the bus is

considered busy.

The next byte of data transmitted after START contains the slave address in the first 7 bits, and the 8th bit tells whether

the Master is receiving data from the slave or is transmitting data to the slave.

After a start condition and when an address is sent, each device in the system compares the first 7 bits with its address.

If the device’s address matches the sent address, then the device considers itself addressed by the Master.

The 9th clock pulse following the slave address byte (and each subsequent byte) is the acknowledge (ACK). The

transmitter must release the SDA line during the ACK period. The receiver must then pull the data line low, so that it

remains stable low during the high period of the acknowledge clock period.

A Master may also issue a repeated START during a data transfer. The MMA8653FC expects repeated STARTs to be

used to randomly read from specific registers.

A low-to-high transition on the SDA line while the SCL line is high is defined as a stop condition (STOP). A data transfer

is always terminated by a STOP.

The MMA8653FC's standard slave address is 0011101 or 0x01D. The slave addresses are factory programmed; alternate

addresses are available upon request.

5.8.1

Single byte read

The transmission of an 8-bit command begins on the falling edge of SCL. After the 8 clock cycles are used to send the

command, note that the data returned is sent with the MSB first after the data is received. Figure 11 "Single Byte Read

timing (I2C)" shows the timing diagram for the accelerometer 8-bit I2C read operation.

The Master (or MCU) transmits a start condition (ST) to the MMA8653FC [slave address (0x1D), with the R/W bit set to

“0” for a write], and the MMA8653FC sends an acknowledgement.

Table 10. Serial Interface pins

Pin Name

Pin Description

Notes

SCL

I2C Serial Clock

There are two signals associated with the I2C bus; the Serial Clock Line (SCL) and the

Serial Data line (SDA).

• SDA is a bidirectional line used for sending and receiving the data to/from the interface.

• External pullup resistors connected to VDDIO are expected for SDA and SCL. When the bus

is free, both SCL and SDA lines are high.

SDA

I2C Serial Data

Table 11. I2C Device address sequence

Command

[6:0]

Device address

[6:0]

Device address

R/W

8-bit final

value

Read

0011101

0x1D

0x3B

Write

0011101

0x1D

0x3A

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