LTC4271 datasheet(21/30 Pages) LINER

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LTC4274A/LTC4274C

4274acfc

APPLICATIONS INFORMATION

802.3at 2-Event Classification

The 802.3at specification defines two methods of classify-

ing a Type 2 PD. The LTC4274A supports 802.3at 2-event

classification. The LTC4274C does not support 2-event

classification.

One method adds extra fields to the Ethernet LLDP data

protocol; although the LTC4274A/LTC4274C is compatible

with this classification method, it cannot perform clas-

sification directly since it doesn’t have access to the data

path. LLDP classification requires the PSE to power the

PD as a standard 802.3af (Type 1) device. It then waits

for the host to perform LLDP communication with the PD

and update the PSE port data. The LTC4274A/LTC4274C

supports changing the ILIM and ICUT levels on the fly, al-

lowing the host to complete LLDP classification.

The second 802.3at classification method, known as

2-event classification or ping-pong, is supported by the

LTC4274A. A Type 2 PD that is requesting more than 13W

will indicate Class 4 during normal 802.3af classification.

If the LTC4274A sees Class 4, it forces the port to a speci-

fied lower voltage (called the mark voltage, typically 9V),

pauses briefly, and then re-runs classification to verify the

Class 4 reading (Figure 1). It also sets a bit in the High

Power Status register to indicate that it ran the second

classification cycle. The second cycle alerts the PD that

it is connected to a Type 2 PSE which can supply Type 2

power levels.

2-event ping-pong classification is enabled by setting a bit

in the port’s High Power Mode register. Note that a ping-

pong enabled port only runs the second classification cycle

when it detects a Class 4 device; if the first cycle returns

Class 0 to 3, the port assumes it is connected to a Type 1

PD and does not run the second classification cycle.

Invalid Type 2 Class Combinations

The 802.3at specification defines a Type 2 PD class sig-

nature as two consecutive Class 4 results; a Class 4 fol-

lowed by a Class 0-3 is not a valid signature. In AUTO pin

mode, the LTC4274A will power a detected PD regardless

of the classification results, with one exception: if the PD

presents an invalid Type 2 signature (Class 4 followed by

Class 0 to 3), the LTC4274A will not provide power and

will restart the detection process. To aid in diagnosis, the

Port Status register will always report the results of the

last class pulse, so, for example, an invalid Class 4–Class 2

combination would report a second class pulse was run

in the High Power Status register (which implies that the

first cycle found Class 4), and Class 2 in the Port Status

POWER CONTROL

External MOSFET, Sense Resistor Summary

The primary function of the LTC4274A/LTC4274C is to

control the delivery of power to the PSE port. It does this

by controlling the gate drive voltage of an external power

MOSFET while monitoring the current via an external

sense resistor and the output voltage at the OUT pin. This

circuitry serves to couple the raw VEE input supply to the

port in a controlled manner that satisfies the PD’s power

needs while minimizing power dissipation in the MOSFET

and disturbances on the VEE backplane.

The LTC4274A/LTC4274C is designed to use 0.25Ω sense

resistors to minimize power dissipation. It also supports

0.5Ω sense resistors, which are the default when LTC4258/

LTC4259A compatibility is desired.

Inrush Control

Once the command has been given to turn on a port, the

LTC4274A/LTC4274C ramps up the GATE pin of the port’s

external MOSFET in a controlled manner. Under normal

power-up circumstances, the MOSFET gate will rise until

the port current reaches the inrush current limit level

(typically 450mA), at which point the GATE pin will be

servoed to maintain the specified IINRUSH current. During

this inrush period, a timer (tSTART) runs. When output

charging is complete, the port current will fall and the GATE

pin will be allowed to continue rising to fully enhance the

MOSFET and minimize its on-resistance. The final VGS is

nominally 12V. The inrush period is maintained until the

tSTART timer expires. At this time if the inrush current limit

level is still exceeded the port will be turned back off and

a tSTART fault reported.

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