LTC6945 datasheet(8/36 Pages) LINER

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LTC2270

2270f

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Digital Data Outputs (LVDS Mode)

ENC to Data Delay

CL = 5pF (Note 8)

1.1

1.8

3.2

ENC to CLKOUT Delay

CL = 5pF (Note 8)

1.5

2.7

tSKEW

DATA to CLKOUT Skew

tD – tC (Note 8)

0.3

0.6

Pipeline Latency

6.5

Cycles

SPI Port Timing (Note 8)

tSCK

SCK Period

Write Mode

Readback Mode, CSDO = 20pF, RPULLUP = 2k

250

CS to SCK Setup Time

5ns

SCK to CS Setup Time

5ns

tDS

SDI Setup Time

5ns

tDH

SDI Hold Time

5ns

tDO

SCK Falling to SDO Valid

Readback Mode, CSDO = 20pF, RPULLUP = 2k

125

TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 5)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND with GND and OGND

shorted (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above VDD, they

will be clamped by internal diodes. This product can handle input currents

of greater than 100mA below GND or above VDD without latchup.

Note 4: When these pin voltages are taken below GND they will be

clamped by internal diodes. When these pin voltages are taken above VDD

they will not be clamped by internal diodes. This product can handle input

currents of greater than 100mA below GND without latchup.

Note 5: VDD = OVDD = 1.8V, fSAMPLE = 20MHz, LVDS outputs, differential

ENC+/ENC– = 2VP-P sine wave, input range = 2.1VP-P with differential drive,

unless otherwise noted.

Note 6: Integral nonlinearity is defined as the deviation of a code from a

best fit straight line to the transfer curve. The deviation is measured from

the center of the quantization band.

Note 7: Offset error is the offset voltage measured from –0.5 LSB when

the output code flickers between 0000 0000 0000 0000 and 1111 1111

1111 1111 in 2’s complement output mode.

Note 8: Guaranteed by design, not subject to test.

Note 9: VDD = 1.8V, fSAMPLE = 20MHz, CMOS outputs, ENC+ = single-ended

1.8V square wave, ENC– = 0V, input range = 2.1VP-P with differential drive,

5pF load on each digital output unless otherwise noted. The supply current

and power dissipation specifications are totals for the entire IC, not per

channel.

Note 10: Recommended operating conditions.

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