DAC5674IPHPR datasheet(21/39 Pages) TI1

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DAC5674

SLWS148A − SEPTEMBER 2003 − REVISED OCTOBER 2005

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PFD

ref

ICO

Fref

Fvco

LPF

DAC5674

External Loop Filter

Figure 22. PLL Functional Block Diagram

Table 5. DAC5674 Evaluation Board PLL Loop Filter Parameters

N(1)

PHASE MARGIN (DEGREES)

BANDWIDTH (MHZ)

1.6

1.4

0.7

0.4

(1) N is the VCO divide-down factor from prescale and interpolation.

Non-Harmonic Clock-Related Spurious Signals

In interpolating DACs, imperfect isolation between the digital and DAC clock circuits generates spurious signals

at frequencies related to the DAC clock rate. The digital interpolation filters in these DACs run at subharmonic

frequencies of the output rate clock, where these frequencies are fDAC/2 , N = 1,2. For example, for 2×

interpolation only one interpolation filter runs at fDAC/2; for 4× interpolation, on the other hand, two interpolation

filters run at fDAC/2 and fDAC/4. These lower-speed clocks for the interpolation filter mix with the DAC clock

circuit and create spurious images of the wanted signal and second Nyquist-zone image at offsets of fDAC/2N.

Figure 23 shows the location of the largest spurious signals for 4

× interpolation for a real signal. With a real

output signal, there is no distinction between negative and positive frequencies, and therefore the signals that

appear at negative frequencies wrap and potentially fall near the wanted signal. In particular, at IFs near fDAC/8,

fDAC/4, and fDAC × 3/4 (50 MHz, 100 MHz, and 150 MHz in this example), the mixing effect results in spurious

signals falling near the wanted signal, which may present a problem depending on the system application. For

a frequency-symmetric signal (such as a single WCDMA or CDMA carrier), operating at exactly fDAC/8, fDAC/4

and fDAC × 3/4, the spurious signal falls completely inside the wanted signal, which produces a clean spectrum

but may result in degradation of the signal quality.

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