поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

SL74HC597D датащи(PDF) 5 Page - System Logic Semiconductor

номер детали SL74HC597D
подробное описание детали  8-Bit Serial or Parallel-Input/ Serial-Output Shift Register with Input Latch(High-Performance Silicon-Gate CMOS)
PDF  9 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  SLS [System Logic Semiconductor]
домашняя страница  http://www.slsemicon.co.kr/e_index.htm
Logo SLS - System Logic Semiconductor

SL74HC597D датащи(HTML) 5 Page - System Logic Semiconductor

  SL74HC597D Datasheet HTML 1Page - System Logic Semiconductor SL74HC597D Datasheet HTML 2Page - System Logic Semiconductor SL74HC597D Datasheet HTML 3Page - System Logic Semiconductor SL74HC597D Datasheet HTML 4Page - System Logic Semiconductor SL74HC597D Datasheet HTML 5Page - System Logic Semiconductor SL74HC597D Datasheet HTML 6Page - System Logic Semiconductor SL74HC597D Datasheet HTML 7Page - System Logic Semiconductor SL74HC597D Datasheet HTML 8Page - System Logic Semiconductor SL74HC597D Datasheet HTML 9Page - System Logic Semiconductor  
Zoom Inzoom in Zoom Outzoom out
 5 / 9 page
background image
SL74HC597
System Logic
Semiconductor
SLS
TIMING REQUIREMENTS(C
L=50pF,Input t r=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25
°C to
-55
°C
≤85°C
≤125°C
Unit
tsu
Minimum Setup Time, Parallel Data
Inputs A -H to Latch Clock
(Figure 5)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tsu
Minimum Setup Time, Serial Data
Input SA to Shift Clock (Figure 6)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tsu
Minimum Setup Time, Serial
Shift/Parallel Load to Shift Clock
(Figure 7)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
th
Minimum Hold Time, Latch Clock to
Parallel Data Inputs A-H
(Figure 5)
2.0
4.5
6.0
25
5
5
30
6
6
40
8
7
ns
th
Minimum Hold Time, Shift Clock to
Serial Data Input SA (Figure 6)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
trec
Minimum Recovery Time, Reset
Inactive to Shift Clock (Figure 3)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tw
Minimum Pulse Width, Latch Clock
and Shift Clock (Figures 1 and 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tw
Minimum Pulse Width, Reset (Figure
3)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tw
Minimum Pulse Width, Serial
Shift/Parallel Load (Figure 4)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns



Html Pages

1 2 3 4 5 6 7 8 9


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com