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AD9518-2ABCPZ датащи(PDF) 43 Page - Analog Devices |
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AD9518-2ABCPZ датащи(HTML) 43 Page - Analog Devices |
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43 / 64 page ![]() Data Sheet AD9518-2 Rev. C | Page 43 of 64 CS SCLK SDIO tHIGH tLOW tCLK tS tDS tDH tC BIT N BIT N + 1 Figure 51. Serial Control Port Timing Diagram—Write Table 40. Serial Control Port Timing Parameter Description tDS Setup time between data and rising edge of SCLK tDH Hold time between data and rising edge of SCLK tCLK Period of the clock tS Setup time between CS falling edge and SCLK rising edge (start of communication cycle) tC Setup time between SCLK rising edge and CS rising edge (end of communication cycle) tHIGH Minimum period that SCLK should be in a logic high state tLOW Minimum period that SCLK should be in a logic low state tDV SCLK to valid SDIO and SDO (see Figure 49) |
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