AD9518-2ABCPZ datasheet(32/64 Pages) AD

32 / 64 page

AD9518-2

Data Sheet

Rev. C | Page 32 of 64

The holdover function senses the logic level of the LD pin as a

condition to enter holdover. The signal at LD can be from the

DLD, ALD, or current source LD mode. It is possible to disable

the LD comparator (Register 0x01D[3]), which causes the holdover

function to always sense LD as high.

If DLD is used, it is possible for the DLD signal to chatter some

while the PLL is reacquiring lock. The holdover function may

retrigger, thereby preventing the holdover mode from ever

terminating. Use of the current source lock detect mode is

recommended to avoid this situation (see the Current Source

Digital Lock Detect section).

Once in holdover mode, the charge pump stays in a high

impedance state as long as there is no reference clock present.

As in the external holdover mode, the B counter (in the N divider)

is reset synchronously with the charge pump leaving the high

impedance state on the reference path PFD event. This helps to

align the edges out of the R and N dividers for faster settling of

the PLL and to reduce frequency errors during settling. Because

the prescaler is not reset, this feature works best when the B and

R numbers are close because this results in a smaller phase

difference for the loop to settle out.

After leaving holdover, the loop then reacquires lock and the

LD pin must charge (if Register 0x01D[3] = 1) before it can

re-enter holdover (CP high impedance).

The holdover function always responds to the state of the

currently selected reference (Register 0x01C). If the loop loses

lock during a reference switchover (see the Reference Switchover

section), holdover is triggered briefly until the next reference

clock edge at the PFD.

The following registers affect automatic/internal holdover:

•

the number of consecutive PFD cycles with edges inside the

lock detect window that are required for the DLD indicator

to indicate lock. This impacts the time required before the

LD pin can begin to charge, as well as the delay from the end

of a holdover event until the holdover function can be

re-engaged.

•

set to 0b to enable the DLD circuit. Automatic/internal hold-

over does not operate correctly without the DLD function

enabled.

•

bits to 000100b for the current source lock detect mode

if using the LD pin comparator. Load the LD pin with

a capacitor of an appropriate value.

•

0 = disable. When disabled, the holdover function always

senses the LD pin as high.

•

function. If holdover is disabled, both external and

automatic/internal holdover are disabled.

For example, to use automatic holdover with the following:

•

Automatic reference switchover, prefer REF1

•

Digital lock detect: five PFD cycles, high range window

•

Automatic holdover using the LD pin comparator

Set the following registers (in addition to the normal PLL registers):

•

mode.

•

REF1 (active low).

•

buffers.

•

mode.

•

(VCO calibration must be complete before this bit is

enabled.)

•

Connect REFMON pin to REFSEL pin.

Frequency Status Monitors

The AD9518 contains three frequency status monitors that are

used to indicate if the PLL reference (or references in the case of

single-ended mode) and the VCO have fallen below a threshold

frequency. A diagram showing their location in the PLL is shown

in Figure 39. The VCO status frequency monitor is also capable

of monitoring the CLK input if the CLK input is selected as the

input to the N divider.

The PLL reference frequency monitors have two threshold

frequencies: normal and extended (see Table 15). The reference

frequency monitor thresholds are selected in Register 0x01A

The frequency monitor status can be found in Register 0x01F,

Bits[3:1].

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