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33982 датащи(PDF) 32 Page - Freescale Semiconductor, Inc |
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33982 датащи(HTML) 32 Page - Freescale Semiconductor, Inc |
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32 / 36 page ![]() Analog Integrated Circuit Device Data 32 Freescale Semiconductor 33982 ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 4.0) ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 4.0) Introduction This thermal addendum is provided as a supplement to the 33982 technical datasheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application, and packaging information is provided in the datasheet. Packaging and Thermal Considerations This package is a dual die package. There are two heat sources in the package independently heating with P1 and P2. This results in two junction temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn. For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference temperature while only heat source 1 is heating with P1. For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the reference temperature while heat source 2 is heating with P2. This applies to RθJ21 and RθJ22, respectively. The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below. Standards Figure 13. Surface Mount for Power PQFN with Exposed Pads High Side Switch 33982 98ARL10521D 16-PIN PQFN 12 mm x 12 mm Note For package dimensions, refer to 98ARL10521D. TJ1 TJ2 = RθJA11 RθJA21 RθJA12 RθJA22 . P1 P2 Table 19. Thermal Performance Comparison Thermal Resistance 1 = Power Chip, 2 = Logic Chip [ °C/W] m = 1, n = 1 m = 1, n = 2 m = 2, n = 1 m = 2, n = 2 RθJAmn (1), (2) 20 16 39 RθJBmn (2), (3) 62.0 26 RθJAmn (1), (4) 53 40 73 RθJCmn (5) <0.5 0.0 1.0 Notes: 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-7and JESD51-5. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the power outputs. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the exposed pad, “infinite” heat sink attached to exposed pad. Note: Recommended via diameter is 0.5 mm. PTH (plated through hole) via must be plugged / filled with epoxy or solder mask in order to minimize void formation and to avoid any solder wicking into the via. 1.0 1.0 0.2 0.2 * All measurements are in millimeters |
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