11

SP791DS/08

SP791 Low Power Microprocessor Supervisory with Battery Switch-Over

© Copyright 2000 Sipex Corporation

The 10ns maximum CE propagation from CE

IN

most

µPs.

CHIP-ENABLE INPUT

RESET is asserted.

below 4.65V, CE IN assumes a high impedance

15

µs after RESET is asserted, whichever

occurs first, (Figure 7).

high impedance until RESET is deasserted.

In the high-impedance mode, the leakage

currents into this input are less than 1

µA over

temperature. In the low-impedance mode, the

Ω resistor

The propagation delay through the CE

transmission gate depends on both the source

Capacitance graph in the Typical Operating

Characteristics). The CE propagation delay is

Ω driver with 50pF

load capacitance as in Figure 8. For minimum

propagation delay, minimize the capacitive load

driver.

CHIP-ENABLE OUTPUT

is equivalent to 65

Ω in series with the source

Ω

transmission gate is enabled.

Figure 8. CE Propagation Delay Test Circuit

Figure 7. Reset and Chip-Enable Timing

+5V

Vcc

50

Ω Driver

GND

50pF

Corporation

Vcc

RESET

15

µs

100

µs

100

µs

RESET

THRESHOLD