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TLE4470GS датащи(PDF) 14 Page - Siemens Semiconductor Group |
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TLE4470GS датащи(HTML) 14 Page - Siemens Semiconductor Group |
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14 / 22 page ![]() TLE 4470 Semiconductor Group 14 1998-11-01 Input, Output The input capacitor C I is necessary for compensating line influences. Using a resistor of approx. 1 Ω in series with C I, the LC circuit of input inductivity and input capacitance can be damped. To stabilize the regulation circuits of the stand-by and main regulator, output capacitors C Q1 and CQ2 are necessary. Stability is guaranteed at values CQ1 ≥ 6 µF & C Q2 ≥ 10 µF, both with an ESR ≤ 10 Ω within the operating temperature range. For the TLE 4470 G (P-DSO-20-6) the output voltage V Q2 of the main regulator can be adjusted to 5 V ≤ V Q2rated ≤ 20 V by connecting an external voltage divider to the voltage adjust pin VA. For V Q2 = 5 V the voltage adjust pin has to be connected directly to the main output. For calculating V Q or R1 & R2 respectively the following equations can be used: V Q = Vref × (R1 + R2) / R2 or R 1 = R × (VQ / Vref) R 2 = R × R1 / (R1 – R) Definitions: R = R 1 // R2 ; R ≈ 100 kΩ V ref = Output voltage of stand by regulator, typical 5 V Disable The main regulator of the TLE 4470 can be switched OFF by a voltage of 2.3 V at pin DIS. Reducing this voltage below 1.4 V will switch ON the main regulator again. Reset Timing The power-on reset delay time is defined by the charging time of an external capacitor C d which can be calculated as follows: C d = (∆td × Id) / ∆V Definitions: C d = delay capacitor ∆t d = delay time I d = charge current, typical 5 µA ∆V= V dt, typical 1.8 V V dt = upper delay switching threshold at Cd for reset delay time The reset reaction time t rr is the time it takes the voltage regulator to set the reset out LOW after the output voltage has dropped below the reset threshold. It is typically 2 µs for delay capacitor of 100 nF. For other values for C d the reaction time can be estimated using the following equation: t rr ≈ 20 s/F × Cd |
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