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MMA6519KW датащи(PDF) 14 Page - Freescale Semiconductor, Inc |
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MMA6519KW датащи(HTML) 14 Page - Freescale Semiconductor, Inc |
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14 / 56 page ![]() Sensor 14 Freescale Semiconductor, Inc. MMA65xx 3.1.4 Part Number Register (PN) The part number register is a one time programmable, read only register which contains two digits of the device part number to identify the axis and range information. The contents of this register have no impact on device operation or performance. 3.1.5 Device Control Register (DEVCTL The device control register is a read-write register which contains device control operations. The upper 2 bits of this register can be written during both initialization and normal operation. Bits 5 through 0 can be programmed during initialization and then are ignored once the ENDINIT bit is set. 3.1.5.1 Reset Control (RES_1, RES_0) A series of three consecutive register write operations to the reset control bits in the DEVCTL register will cause a device reset. To reset the internal digital circuitry, the following register write operations must be performed in the order shown below. The reg- ister write operations must be consecutive SPI commands in the order shown or the device will not be reset. The response to the Register Write returns ‘0’ for RES_1 and RES_0, and the existing register value bits 5 through 0. A Reg- ister Read of RES_1 and RES_0 returns ‘0’ and terminates the reset sequence. If ENDINIT is cleared, the bits 2 through 0 in the DEVCTL register are modified as described in Section 4.4. If ENDINIT is set, a Register Write will not modify bits 2 through 0 and the response to a Register Read or Write will include the last successful written values for these bits. Table 6. Part Number Register Location Bit Address Register 76543210 $08 PN PN[7] PN[6] PN[5] PN[4] PN[3] PN[2] PN[1] PN[0] PN Register Value X-Axis Range Section 2.4 Y-Axis Range Section 2.4 Decimal HEX 219 $DB 80 80 225 $E1 105 105 227 $E3 120 120 Table 7. Device Control Register Location Bit Address Register 7 6 5 4 3 2 1 0 $0A DEVCTL RES_1 RES_0 OCPHASE[1] OCPHASE[0] OFFCFG_EN Reserved Reserved Reserved Reset Value 0 0 000 0 0 0 Register Write to DEVCTL RES_1 RES_0 Effect SPI Register Write 1 0 0 No Effect SPI Register Write 2 1 1 No Effect SPI Register Write 3 0 1 Device RESET |
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