MMA6519KW datasheet(48/56 Pages) FREESCALE

48 / 56 page

Sensor

Freescale Semiconductor, Inc.

MMA65xx

4.3

Acceleration Data Transfers

Twelve bit Acceleration data requests are initiated when the Acceleration bit of the SPI command message (A) is set to a logic

‘1’, and bit D[3] of the SPI command message is set to a logic ‘1’. The Axis Selection bit (AX) selects the type of acceleration data

requested, as shown in Table 31.

To verify that the device is configured as expected, each acceleration data request includes the configuration information which

impacts the output data. The requested configuration is compared against the data programmed in the writable register block.

Details are shown in Table 32.

If the data listed in Table 32 does not does not match, an Acceleration Data Request Mismatch failure is detected and no ac-

celeration data is transmitted. Reference Section 4.5.3.1.

Acceleration data request commands include a parity bit (P). Odd parity is employed. The number of logic ‘1’ bits in the accel-

eration data request command must be an odd number.

Acceleration data is transmitted on the next SPI message if and only if all of the following conditions are met:

•

The DEVINIT bit in the DEVSTAT register is not set

•

The DEVRES bit in the DEVSTAT register is not set

•

The IDE bit in the DEVSTAT register is not set (Reference Section 4.5.5)

•

No SPI Error is detected (Reference Section 4.5.1)

•

No MISO Error is detected (Reference Section 4.5.2)

•

No Acceleration Data Request Mismatch failure is detected (Reference Section 4.5.3.1)

•

No Self Test Error is present (reference Section 4.5.5.2)

•

No Offset Monitor Error is present for the requested channel (reference Section 4.5.6)

If the above conditions are met, the device responds with a “valid acceleration data request” response as shown in Table 30.

Otherwise, the device responds as specified in Section 4.5.

Table 31. Acceleration Data Request

Axis Selection Bit (AX)

Data Type

X-Axis Acceleration Data

Y-Axis Acceleration Data

Table 32. Acceleration Data Request Configuration Information

Programmable Option

Command Message Bit

Writable Register Information

Raw or Offset Cancelled Data

DEVCFG[7] (OC)

Signed or Unsigned Data

DEVCFG[4] (SD)

Arming Function or PCM Output

ARM

DEVCFG[2] || DEVCFG[1] (A_CFG[2] || A_CFG[1])

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