LTC4253 datasheet(18/36 Pages) LINER

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LTC4252-1/LTC4252-2

LTC4252A-1/LTC4252A-2

425212fd

APPLICATIONS INFORMATION

and eliminates current spikes at insertion. A large external

gate-source capacitor is thus unnecessary for the purpose

of compensating CGD. Instead, a smaller value (≥ 10nF)

capacitor CC is adequate. CC also provides compensation

for the analog current limit loop.

GATE has two comparators: the GATE low comparator

looks for < 0.5V threshold prior to initial timing or a GATE

start-up cycle; the GATE high comparator looks for < 2.8V

relative to VIN and, together with the DRAIN low compara-

tor, sets PWRGD status during GATE startup.

SENSE

The SENSE pin is monitored by the circuit breaker (CB)

comparator, the analog current limit (ACL) amplifier and

the fast current limit (FCL) comparator. Each of these three

measures the potential of SENSE relative to VEE. When

SENSE exceeds 50mV, the CB comparator activates the

230μA TIMER pull-up. At 100mV (60mV for the LTC4252A),

the ACL amplifier servos the MOSFET current and, at

200mV, the FCL comparator abruptly pulls GATE low in

an attempt to bring the MOSFET current under control. If

any of these conditions persists long enough for TIMER

to charge CT to 4V (see Equation 3), the LTC4252 shuts

down and pulls GATE low.

If the SENSE pin encounters a voltage greater than VACL,

the ACL amplifier will servo GATE downwards in an attempt

to control the MOSFET current. Since GATE overdrives the

MOSFET in normal operation, the ACL amplifier needs time

to discharge GATE to the threshold of the MOSFET. For a

mild overload the ACL amplifier can control the MOSFET

current, but in the event of a severe overload the current

may overshoot. At SENSE = 200mV the FCL comparator

takes over, quickly discharging the GATE pin to near VEE

potential. FCL then releases and the ACL amplifier takes

over. All the while TIMER is running. The effect of FCL is

to add a nonlinear response to the control loop in favor

of reducing MOSFET current.

Owing to inductive effects in the system, FCL typically

overcorrects the current limit loop and GATE undershoots.

A zero in the loop (resistor RC in series with the gate ca-

pacitor) helps the ACL amplifier to recover.

SHORT-CIRCUIT OPERATION

Circuit behavior arising from a load side low impedance

short is shown in Figure 6 for the LTC4252. Initially, the

current overshoots the fast current limit level of VSENSE =

200mV (Trace 2) as the GATE pin works to bring VGS under

control (Trace 3). The overshoot glitches the backplane

in the negative direction and when the current is reduced

to 100mV/RS, the backplane responds by glitching in the

positive direction.

TIMER commences charging CT (Trace 4) while the analog

current limit loop maintains the fault current at 100mV/RS,

which in this case is 5A (Trace 2). Note that the backplane

voltage (Trace 1) sags under load. Timer pull-up is ac-

celerated by VOUT. When CT reaches 4V, GATE turns off,

PWRGD pulls high, the load current drops to zero and the

backplane rings up to over 100V. The transient associated

with the GATE turn off can be controlled with a snubber to

reduce ringing and a transient voltage suppressor (such as

Diodes Inc. SMAT70A) to clip off large spikes. The choice

of RC for the snubber is usually done experimentally. The

value of the snubber capacitor is usually chosen between

10 to 100 times the MOSFET COSS. The value of the snub-

ber resistor is typically between 3Ω to 100Ω.

425212 F06

–48RTN

50V/DIV

GATE

10V/DIV

SENSE

200mV/DIV

TIMER

5V/DIV

0.5ms/DIV

FAST CURRENT LIMIT

SUPPLY RING OWING TO

CURRENT OVERSHOOT

SUPPLY RING OWING TO

MOSFET TURN OFF

ANALOG CURRENT LIMIT

ONSET OF OUTPUT SHORT-CIRCUIT

CTIMER RAMP

LATCH OFF

Figure 6. Output Short-Circuit Behavior of LTC4252

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